commit 5dca61397878a7207986455b42fa2117fbf78000
author Andrew Trick <atrick@apple.com> Thu Jul 25 07:26:26 2013 +0000
committer Andrew Trick <atrick@apple.com> Thu Jul 25 07:26:26 2013 +0000
tree f77d28d7b141298d624cbe9b6aaa805eafc92ec3
parent 27ce44d3b4d2111c636fd802920dd0c35b7d6829

Dump LIS before regalloc. MI sched changes them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187107 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineScheduler.cpp

diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 2ee8775..19e86d7 100644
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -204,7 +204,7 @@
   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 
   if (VerifyScheduling) {
-    DEBUG(LIS->print(dbgs()));
+    DEBUG(LIS->dump());
     MF->verify(this, "Before machine scheduling.");
   }
   RegClassInfo->runOnMachineFunction(*MF);
@@ -294,7 +294,7 @@
     Scheduler->finishBlock();
   }
   Scheduler->finalizeSchedule();
-  DEBUG(LIS->print(dbgs()));
+  DEBUG(LIS->dump());
   if (VerifyScheduling)
     MF->verify(this, "After machine scheduling.");
   return true;