Revert r118457 and r118458. These won't hold for GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index fe6bd34..296a5c9 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -378,11 +378,14 @@
unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &) const {
- // {12-8} = Rd
- // {7-0} = count
- unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
- Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
+ SmallVectorImpl<MCFixup> &Fixups) const {
+ // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
+ // register in the list, set the corresponding bit.
+ unsigned Binary = 0;
+ for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
+ unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
+ Binary |= 1 << regno;
+ }
return Binary;
}