A few inline asm cleanups:
- Make targetlowering.h fit in 80 cols.
- Make LowerAsmOperandForConstraint const.
- Make lowerXConstraint -> LowerXConstraint
- Make LowerXConstraint return a const char* instead of taking a string byref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index f69f046..6c15ff9 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1534,14 +1534,12 @@
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
-void TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
- std::string& s) const {
+const char *TargetLowering::LowerXConstraint(MVT::ValueType ConstraintVT) const{
if (MVT::isInteger(ConstraintVT))
- s = "r";
- else if (MVT::isFloatingPoint(ConstraintVT))
- s = "f"; // works for many targets
- else
- s = "";
+ return "r";
+ if (MVT::isFloatingPoint(ConstraintVT))
+ return "f"; // works for many targets
+ return 0;
}
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
@@ -1549,7 +1547,7 @@
void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
char ConstraintLetter,
std::vector<SDOperand> &Ops,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
switch (ConstraintLetter) {
default: break;
case 'X': // Allows any operand; labels (basic block) use this.
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 09779be..d3f410e 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3984,7 +3984,7 @@
/// vector. If it is invalid, don't add anything to Ops.
void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
std::vector<SDOperand>&Ops,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
SDOperand Result(0,0);
switch (Letter) {
default: break;
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index bd13baf..8ea419d 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -293,7 +293,7 @@
virtual void LowerAsmOperandForConstraint(SDOperand Op,
char ConstraintLetter,
std::vector<SDOperand> &Ops,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 8d37663..5b606f2 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -6280,17 +6280,18 @@
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
-void X86TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
- std::string& s) const {
+const char *X86TargetLowering::
+LowerXConstraint(MVT::ValueType ConstraintVT) const {
+ // FP X constraints get lowered to SSE1/2 registers if available, otherwise
+ // 'f' like normal targets.
if (MVT::isFloatingPoint(ConstraintVT)) {
if (Subtarget->hasSSE2())
- s = "Y";
- else if (Subtarget->hasSSE1())
- s = "x";
- else
- s = "f";
- } else
- return TargetLowering::lowerXConstraint(ConstraintVT, s);
+ return "Y";
+ if (Subtarget->hasSSE1())
+ return "x";
+ }
+
+ return TargetLowering::LowerXConstraint(ConstraintVT);
}
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
@@ -6298,7 +6299,7 @@
void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
char Constraint,
std::vector<SDOperand>&Ops,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
SDOperand Result(0, 0);
switch (Constraint) {
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 1d6d43f..6b02f33 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -371,15 +371,14 @@
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
- virtual void lowerXConstraint(MVT::ValueType ConstraintVT,
- std::string&) const;
+ virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDOperand Op,
char ConstraintLetter,
std::vector<SDOperand> &Ops,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// getRegForInlineAsmConstraint - Given a physical register constraint
/// (e.g. {edx}), return the register number and the register class for the