Reapply 53476 and 53480, with a fix so that it properly updates
the BB member to the current basic block after emitting
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53567 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 02f20f9..982bbab 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -1082,7 +1082,7 @@
}
/// EmitSchedule - Emit the machine code in scheduled order.
-void ScheduleDAG::EmitSchedule() {
+MachineBasicBlock *ScheduleDAG::EmitSchedule() {
bool isEntryBB = &MF->front() == BB;
if (isEntryBB && !SchedLiveInCopies) {
@@ -1118,6 +1118,8 @@
if (isEntryBB && SchedLiveInCopies)
EmitLiveInCopies(MF->begin());
+
+ return BB;
}
/// dump - dump the schedule.
@@ -1133,9 +1135,12 @@
/// Run - perform scheduling.
///
-MachineBasicBlock *ScheduleDAG::Run() {
+void ScheduleDAG::Run() {
Schedule();
- return BB;
+
+ DOUT << "*** Final schedule ***\n";
+ DEBUG(dumpSchedule());
+ DOUT << "\n";
}
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 8a1dade..39aadd5 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -99,13 +99,6 @@
ListScheduleTopDown();
AvailableQueue->releaseState();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
-
- // Emit in scheduled order
- EmitSchedule();
}
//===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 287e8c5..098b799 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -204,13 +204,6 @@
if (!Fast)
CommuteNodesToReducePressure();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
-
- // Emit in scheduled order
- EmitSchedule();
}
/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b4b81cd..bf68040 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5284,10 +5284,11 @@
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Lowered selection DAG:\n";
DEBUG(DAG.dump());
+ std::string GroupName = "Instruction Selection and Scheduling";
// Run the DAG combiner in pre-legalize mode.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Combining 1");
+ NamedRegionTimer T("DAG Combining 1", GroupName);
DAG.Combine(false, *AA);
} else {
DAG.Combine(false, *AA);
@@ -5304,7 +5305,7 @@
}
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Legalization");
+ NamedRegionTimer T("DAG Legalization", GroupName);
DAG.Legalize();
} else {
DAG.Legalize();
@@ -5315,7 +5316,7 @@
// Run the DAG combiner in post-legalize mode.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("DAG Combining 2");
+ NamedRegionTimer T("DAG Combining 2", GroupName);
DAG.Combine(true, *AA);
} else {
DAG.Combine(true, *AA);
@@ -5332,24 +5333,41 @@
// Third, instruction select all of the operations to machine code, adding the
// code to the MachineBasicBlock.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Selection");
+ NamedRegionTimer T("Instruction Selection", GroupName);
InstructionSelect(DAG);
} else {
InstructionSelect(DAG);
}
+ // Schedule machine code.
+ ScheduleDAG *Scheduler;
+ if (TimePassesIsEnabled) {
+ NamedRegionTimer T("Instruction Scheduling", GroupName);
+ Scheduler = Schedule(DAG);
+ } else {
+ Scheduler = Schedule(DAG);
+ }
+
// Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Scheduling");
- ScheduleAndEmitDAG(DAG);
+ NamedRegionTimer T("Instruction Creation", GroupName);
+ BB = Scheduler->EmitSchedule();
} else {
- ScheduleAndEmitDAG(DAG);
+ BB = Scheduler->EmitSchedule();
+ }
+
+ // Free the scheduler state.
+ if (TimePassesIsEnabled) {
+ NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
+ delete Scheduler;
+ } else {
+ delete Scheduler;
}
// Perform target specific isel post processing.
if (TimePassesIsEnabled) {
- NamedRegionTimer T("Instruction Selection Post Processing");
+ NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
InstructionSelectPostProcessing(DAG);
} else {
InstructionSelectPostProcessing(DAG);
@@ -5597,10 +5615,10 @@
}
-//===----------------------------------------------------------------------===//
-/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
+/// Schedule - Pick a safe ordering for instructions for each
/// target node in the graph.
-void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
+///
+ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
@@ -5610,12 +5628,11 @@
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel);
- BB = SL->Run();
+ ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
+ Scheduler->Run();
- if (ViewSUnitDAGs) SL->viewGraph();
-
- delete SL;
+ if (ViewSUnitDAGs) Scheduler->viewGraph();
+ return Scheduler;
}