commit 5e84e3ccaa555bd48ecca384e93e55abd76fb40a
author Andrew Trick <atrick@apple.com> Sat Mar 05 09:18:16 2011 +0000
committer Andrew Trick <atrick@apple.com> Sat Mar 05 09:18:16 2011 +0000
tree 015f43fdcf2627b5ddc7e9d416ee10b21ed6f08a
parent ece96f5713e14b705d415eb95fe57c5fff841626

Fix for -sched-high-latency-cycles in sched=list-ilp mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127071 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 25f0927..67005d7 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -515,7 +515,9 @@
   }
 
   if (!InstrItins || InstrItins->isEmpty()) {
-    if (SU->getNode() && TII->isHighLatencyDef(SU->getNode()->getOpcode()))
+    SDNode *N = SU->getNode();
+    if (N && N->isMachineOpcode() &&
+        TII->isHighLatencyDef(N->getMachineOpcode()))
       SU->Latency = HighLatencyCycles;
     else
       SU->Latency = 1;