Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index 3f61d74..727fd61 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -16,9 +16,10 @@
#ifndef LLVM_CODEGEN_ASMPRINTER_H
#define LLVM_CODEGEN_ASMPRINTER_H
+#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/DataTypes.h"
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/Target/TargetMachine.h"
#include <set>
namespace llvm {
@@ -66,7 +67,7 @@
std::set<const GlobalValue*> ExtWeakSymbols;
/// OptLevel - Generating code at a specific optimization level.
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
public:
/// Output stream on which we're printing assembly code.
///
@@ -111,7 +112,7 @@
protected:
explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V);
+ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
public:
virtual ~AsmPrinter();
diff --git a/include/llvm/CodeGen/DwarfWriter.h b/include/llvm/CodeGen/DwarfWriter.h
index 5641407..e4e4850 100644
--- a/include/llvm/CodeGen/DwarfWriter.h
+++ b/include/llvm/CodeGen/DwarfWriter.h
@@ -21,6 +21,7 @@
#define LLVM_CODEGEN_DWARFWRITER_H
#include "llvm/Pass.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
@@ -81,7 +82,7 @@
void EndFunction(MachineFunction *MF);
/// ValidDebugInfo - Return true if V represents valid debug info value.
- bool ValidDebugInfo(Value *V, unsigned OptLevel);
+ bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
/// RecordSourceLine - Register a source line with debug info. Returns a
/// unique label ID used to generate a label and provide correspondence to
diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 84d9819..a231f49 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/GCs.h"
+#include "llvm/Target/TargetMachine.h"
namespace {
struct ForceCodegenLinking {
@@ -42,11 +43,11 @@
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
- (void) llvm::createBURRListDAGScheduler(NULL, 3);
- (void) llvm::createTDRRListDAGScheduler(NULL, 3);
- (void) llvm::createTDListDAGScheduler(NULL, 3);
- (void) llvm::createFastDAGScheduler(NULL, 3);
- (void) llvm::createDefaultScheduler(NULL, 3);
+ (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
}
} ForceCodegenLinking; // Force link by creating a global definition.
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index e02dc7a..1cf64a0 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -16,6 +16,7 @@
#define LLVM_CODEGENSCHEDULERREGISTRY_H
#include "llvm/CodeGen/MachinePassRegistry.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
@@ -32,7 +33,8 @@
class RegisterScheduler : public MachinePassRegistryNode {
public:
- typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
+ typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
+ CodeGenOpt::Level);
static MachinePassRegistry Registry;
@@ -64,27 +66,27 @@
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createFastDAGScheduler - This creates a "fast" scheduler.
///
ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
} // end namespace llvm
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 9060376..74aa8ff 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -20,7 +20,7 @@
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
-
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <vector>
#include <map>
@@ -30,7 +30,6 @@
class AliasAnalysis;
class TargetLowering;
-class TargetMachine;
class MachineModuleInfo;
class DwarfWriter;
class MachineFunction;
@@ -202,7 +201,8 @@
/// certain types of nodes together, or eliminating superfluous nodes. The
/// Level argument controls whether Combine is allowed to produce nodes and
/// types that are illegal on the target.
- void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
+ void Combine(CombineLevel Level, AliasAnalysis &AA,
+ CodeGenOpt::Level OptLevel);
/// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
/// only uses types natively supported by the target. Returns "true" if it
@@ -218,7 +218,7 @@
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
- void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
+ void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
/// RemoveDeadNodes - This method deletes all unreachable nodes in the
/// SelectionDAG.
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index d8802c7..05a0475 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -51,10 +51,11 @@
MachineBasicBlock *BB;
AliasAnalysis *AA;
GCFunctionInfo *GFI;
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
static char ID;
- explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
+ explicit SelectionDAGISel(TargetMachine &tm,
+ CodeGenOpt::Level OL = CodeGenOpt::Default);
virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }
diff --git a/include/llvm/ExecutionEngine/ExecutionEngine.h b/include/llvm/ExecutionEngine/ExecutionEngine.h
index 014473a..5df11f3 100644
--- a/include/llvm/ExecutionEngine/ExecutionEngine.h
+++ b/include/llvm/ExecutionEngine/ExecutionEngine.h
@@ -18,8 +18,9 @@
#include <vector>
#include <map>
#include <string>
-#include "llvm/System/Mutex.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/System/Mutex.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
@@ -84,7 +85,7 @@
// libraries, the JIT and Interpreter set these functions to ctor pointers
// at startup time if they are linked in.
typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
static EECtorFn JITCtor, InterpCtor;
/// LazyFunctionCreator - If an unknown function is needed, this function
@@ -114,7 +115,8 @@
static ExecutionEngine *create(ModuleProvider *MP,
bool ForceInterpreter = false,
std::string *ErrorStr = 0,
- unsigned OptLevel = 3);
+ CodeGenOpt::Level OptLevel =
+ CodeGenOpt::Default);
/// create - This is the factory method for creating an execution engine which
/// is appropriate for the current machine. This takes ownership of the
@@ -127,10 +129,9 @@
static ExecutionEngine *createJIT(ModuleProvider *MP,
std::string *ErrorStr = 0,
JITMemoryManager *JMM = 0,
- unsigned OptLevel = 3);
-
-
-
+ CodeGenOpt::Level OptLevel =
+ CodeGenOpt::Default);
+
/// addModuleProvider - Add a ModuleProvider to the list of modules that we
/// can JIT from. Note that this takes ownership of the ModuleProvider: when
/// the ExecutionEngine is destroyed, it destroys the MP as well.
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index ba688b4..8afd71f 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -68,6 +68,19 @@
};
}
+// Code generation optimization level.
+namespace CodeGenOpt {
+ enum Level {
+ Default,
+ None,
+ One,
+ Two,
+ Size,
+ Aggressive,
+ LTO
+ };
+}
+
//===----------------------------------------------------------------------===//
///
/// TargetMachine - Primary interface to the complete machine description for
@@ -213,7 +226,7 @@
virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
raw_ostream &,
CodeGenFileType,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return FileModel::None;
}
@@ -223,7 +236,7 @@
///
virtual bool addPassesToEmitFileFinish(PassManagerBase &,
MachineCodeEmitter *,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return true;
}
@@ -235,7 +248,7 @@
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &,
MachineCodeEmitter &,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return true;
}
@@ -245,7 +258,7 @@
virtual bool WantsWholeFile() const { return false; }
virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
CodeGenFileType,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return true;
}
};
@@ -260,13 +273,13 @@
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output.
///
- bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
+ bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
public:
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
- /// generation. If OptLevel is 0, the code generator should emit code as fast
+ /// generation. If OptLevel is None, the code generator should emit code as fast
/// as possible, though the generated code may be less efficient. This method
/// should return FileModel::Error if emission of this file type is not
/// supported.
@@ -278,7 +291,7 @@
virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level);
/// addPassesToEmitFileFinish - If the passes to emit the specified file had
/// to be split up (e.g., to add an object writer pass), this method can be
@@ -286,7 +299,7 @@
///
virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
- unsigned OptLevel);
+ CodeGenOpt::Level);
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
/// get machine code emitted. This uses a MachineCodeEmitter object to handle
@@ -296,21 +309,21 @@
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
- unsigned OptLevel);
+ CodeGenOpt::Level);
/// Target-Independent Code Generator Pass Configuration Options.
/// addInstSelector - This method should add any "last minute" LLVM->LLVM
/// passes, then install an instruction selector pass, which converts from
/// LLVM code to machine instructions.
- virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
return true;
}
/// addPreRegAllocPasses - This method may be implemented by targets that want
/// to run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
- virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
@@ -318,14 +331,14 @@
/// want to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
- virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
- virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
@@ -333,7 +346,7 @@
/// addAssemblyEmitter - This pass should be overridden by the target to add
/// the asmprinter, if asm emission is supported. If this is not supported,
/// 'true' should be returned.
- virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
+ virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /* VerboseAsmDefault */, raw_ostream &) {
return true;
}
@@ -341,7 +354,7 @@
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned. If DumpAsm is true, the generated assembly is printed to cerr.
- virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+ virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /*DumpAsm*/, MachineCodeEmitter &) {
return true;
}
@@ -350,7 +363,7 @@
/// a code emitter (without setting flags), if supported. If this is not
/// supported, 'true' should be returned. If DumpAsm is true, the generated
/// assembly is printed to cerr.
- virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /*DumpAsm*/, MachineCodeEmitter &) {
return true;
}