commit 5f2180c53330502eb2f0f5bf3f21a838ad800906
author Vikram S. Adve <vadve@cs.uiuc.edu> Tue May 27 00:05:23 2003 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Tue May 27 00:05:23 2003 +0000
tree fd2e03a6e2409e48c1d145b16ebb8ff41c77003d
parent 49cab03c8149619b5c07e473b08d73b91aefb35c

(1) Added special register class containing (for now) %fsr.
    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/PHIElimination.cpp

diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 11835cb..2149f90 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -165,7 +165,7 @@
         for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
           MachineOperand &MO = PrevInst->getOperand(i);
           if (MO.isVirtualRegister() && MO.getReg() == IncomingReg)
-            if (MO.opIsDef() || MO.opIsDefAndUse()) {
+            if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
               HaveNotEmitted = false;
               break;
             }