commit 5f2316a3b55f88dab2190212210770180a32aa95
author Jakob Stoklund Olesen <stoklund@2pi.dk> Fri Jun 03 20:34:53 2011 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Fri Jun 03 20:34:53 2011 +0000
tree b7cf1543bab66cb34f478ae01a398843834e5b63
parent d365fa9415ce31b5f0a6019b33c6f099a82f4e34

Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/AllocationOrder.cpp

diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp
index 20c7625..0b7cd49 100644
--- a/lib/CodeGen/AllocationOrder.cpp
+++ b/lib/CodeGen/AllocationOrder.cpp
@@ -15,6 +15,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "AllocationOrder.h"
+#include "RegisterClassInfo.h"
 #include "VirtRegMap.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
@@ -23,8 +24,8 @@
 // Compare VirtRegMap::getRegAllocPref().
 AllocationOrder::AllocationOrder(unsigned VirtReg,
                                  const VirtRegMap &VRM,
-                                 const BitVector &ReservedRegs)
-  : Pos(0), Reserved(ReservedRegs) {
+                                 const RegisterClassInfo &RegClassInfo)
+  : Pos(0), RCI(RegClassInfo) {
   const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
   std::pair<unsigned, unsigned> HintPair =
     VRM.getRegInfo().getRegAllocationHint(VirtReg);
@@ -47,7 +48,7 @@
 
   // The hint must be a valid physreg for allocation.
   if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
-               !RC->contains(Hint) || ReservedRegs.test(Hint)))
+               !RC->contains(Hint) || RCI.isReserved(Hint)))
     Hint = 0;
 }
 
@@ -61,7 +62,7 @@
   // Then look at the order from TRI.
   while(Pos != End) {
     unsigned Reg = *Pos++;
-    if (Reg != Hint && !Reserved.test(Reg))
+    if (Reg != Hint && !RCI.isReserved(Reg))
       return Reg;
   }
   return 0;