Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 72f40a0..6dbd9e5 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -513,7 +513,7 @@
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
unsigned oc = MI->getOpcode();
- if (oc == getOpcode(ARMII::LDR)) {
+ if (oc == getOpcode(ARMII::LDRrr)) {
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
@@ -523,6 +523,14 @@
return MI->getOperand(0).getReg();
}
}
+ else if (oc == getOpcode(ARMII::LDRri)) {
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ FrameIndex = MI->getOperand(1).getIndex();
+ return MI->getOperand(0).getReg();
+ }
+ }
else if ((oc == getOpcode(ARMII::FLDD)) ||
(oc == getOpcode(ARMII::FLDS))) {
if (MI->getOperand(1).isFI() &&
@@ -540,7 +548,7 @@
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
unsigned oc = MI->getOpcode();
- if (oc == getOpcode(ARMII::STR)) {
+ if (oc == getOpcode(ARMII::STRrr)) {
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
@@ -550,6 +558,14 @@
return MI->getOperand(0).getReg();
}
}
+ else if (oc == getOpcode(ARMII::STRri)) {
+ if (MI->getOperand(1).isFI() &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ FrameIndex = MI->getOperand(1).getIndex();
+ return MI->getOperand(0).getReg();
+ }
+ }
else if ((oc == getOpcode(ARMII::FSTD)) ||
(oc == getOpcode(ARMII::FSTS))) {
if (MI->getOperand(1).isFI() &&
@@ -602,7 +618,7 @@
if (I != MBB.end()) DL = I->getDebugLoc();
if (RC == ARM::GPRRegisterClass) {
- AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STR)))
+ AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STRrr)))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::DPRRegisterClass) {
@@ -626,7 +642,10 @@
DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == ARM::GPRRegisterClass) {
- Opc = getOpcode(ARMII::STR);
+ if ((Addr.size() > 1) && Addr[1].isImm())
+ Opc = getOpcode(ARMII::STRri);
+ else
+ Opc = getOpcode(ARMII::STRrr);
} else if (RC == ARM::DPRRegisterClass) {
Opc = getOpcode(ARMII::FSTD);
} else {
@@ -651,7 +670,7 @@
if (I != MBB.end()) DL = I->getDebugLoc();
if (RC == ARM::GPRRegisterClass) {
- AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDR)), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDRrr)), DestReg)
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::DPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FLDD)), DestReg)
@@ -671,7 +690,10 @@
DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == ARM::GPRRegisterClass) {
- Opc = getOpcode(ARMII::LDR);
+ if ((Addr.size() > 1) && Addr[1].isImm())
+ Opc = getOpcode(ARMII::LDRri);
+ else
+ Opc = getOpcode(ARMII::LDRrr);
} else if (RC == ARM::DPRRegisterClass) {
Opc = getOpcode(ARMII::FLDD);
} else {
@@ -704,14 +726,14 @@
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
- NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STR)))
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STRrr)))
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
- NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDR)))
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDRrr)))
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |