Use an enumeration to eliminate data relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29249 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 186b041..97eccb2 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -226,7 +226,22 @@
return N;
}
-static unsigned CreateVirtualRegisters(MachineInstr *MI,
+static const TargetRegisterClass *getInstrOperandRegClass(
+ const MRegisterInfo *MRI,
+ const TargetInstrInfo *TII,
+ const TargetInstrDescriptor *II,
+ unsigned Op) {
+ if (Op >= II->numOperands) {
+ assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+ return NULL;
+ }
+ const TargetOperandInfo &toi = II->OpInfo[Op];
+ return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+}
+
+static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
+ MachineInstr *MI,
unsigned NumResults,
SSARegMap *RegMap,
const TargetInstrInfo *TII,
@@ -234,10 +249,10 @@
// Create the result registers for this node and add the result regs to
// the machine instruction.
unsigned ResultReg =
- RegMap->createVirtualRegister(TII->getInstrOperandRegClass(&II, 0));
+ RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
MI->addRegOperand(ResultReg, MachineOperand::Def);
for (unsigned i = 1; i != NumResults; ++i) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(&II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
}
@@ -276,7 +291,8 @@
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II, IIOpNum);
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
@@ -333,7 +349,8 @@
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II, IIOpNum);
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
@@ -389,7 +406,7 @@
// Otherwise, create new virtual registers.
if (NumResults && VRBase == 0)
- VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, TII, II);
+ VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.