commit 619fb527646479ebb031ce1fe0803324c89740d3
author Andrew Lenharth <andrewl@lenharth.org> Mon Jul 04 20:07:21 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Mon Jul 04 20:07:21 2005 +0000
tree 04c21bd0b68035b27e110a76b70507eccea36278
parent 2f5bca5c153b0372bb74b0eda111d8a084983dd9

check the correct VT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22332 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index ed285a3..bef5293 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1642,7 +1642,7 @@
       Select(Chain);
       unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
       //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
-      if (isFP)
+      if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
         BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
       else
         BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);