Use BitVector instead of vector<bool> which can be extremely slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34302 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index 70c189d..362b354 100644
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
namespace llvm {
@@ -54,7 +55,7 @@
typedef IndexedMap<unsigned> Reg2RegMap;
Reg2RegMap r2rMap_;
- std::vector<bool> allocatableRegs_;
+ BitVector allocatableRegs_;
public:
struct CopyRec {
diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h
index 47801a9..6e7e23d 100644
--- a/include/llvm/CodeGen/LiveVariables.h
+++ b/include/llvm/CodeGen/LiveVariables.h
@@ -30,6 +30,7 @@
#define LLVM_CODEGEN_LIVEVARIABLES_H
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/ADT/BitVector.h"
#include <map>
namespace llvm {
@@ -75,7 +76,7 @@
/// through. This is a bit set which uses the basic block number as an
/// index.
///
- std::vector<bool> AliveBlocks;
+ BitVector AliveBlocks;
/// Kills - List of MachineInstruction's which are the last use of this
/// virtual register (kill it) in their basic block.
@@ -111,7 +112,7 @@
/// are actually register allocatable by the target machine. We can not track
/// liveness for values that are not in this set.
///
- std::vector<bool> AllocatablePhysicalRegisters;
+ BitVector AllocatablePhysicalRegisters;
private: // Intermediate data structures
const MRegisterInfo *RegInfo;
diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index 46a2cc3..6d53d51 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -30,6 +30,7 @@
class MachineMove;
class TargetRegisterClass;
class CalleeSavedInfo;
+class BitVector;
/// TargetRegisterDesc - This record contains all of the information known about
/// a particular register. The AliasSet field (if not null) contains a pointer
@@ -240,7 +241,7 @@
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not.
- std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
+ BitVector getAllocatableSet(MachineFunction &MF) const;
const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 83852ca..57a73d2 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -461,7 +461,7 @@
// If the kill happens after the definition, we have an intra-block
// live range.
if (killIdx > defIndex) {
- assert(vi.AliveBlocks.empty() &&
+ assert(vi.AliveBlocks.none() &&
"Shouldn't be alive across any blocks!");
LiveRange LR(defIndex, killIdx, ValNum);
interval.addRange(LR);
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 74d76c1..f862023 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -789,7 +789,7 @@
// is allocatable. To handle this, we mark all unallocatable registers as
// being pinned down, permanently.
{
- std::vector<bool> Allocable = RegInfo->getAllocatableSet(Fn);
+ BitVector Allocable = RegInfo->getAllocatableSet(Fn);
for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
if (!Allocable[i])
PhysRegsUsed[i] = -2; // Mark the reg unallocable.
diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 01295e8..7caaae9 100644
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -14,10 +14,10 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
-
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/ADT/BitVector.h"
using namespace llvm;
@@ -34,8 +34,8 @@
MRegisterInfo::~MRegisterInfo() {}
-std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
- std::vector<bool> Allocatable(NumRegs);
+BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
+ BitVector Allocatable(NumRegs);
for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I;