Add a target hook to add pre- post-regalloc scheduling passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83144 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 9614780..92b648c 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -362,20 +362,28 @@
return true;
}
- /// addPreRegAllocPasses - This method may be implemented by targets that want
- /// to run passes immediately before register allocation. This should return
+ /// addPreRegAlloc - This method may be implemented by targets that want to
+ /// run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
- /// addPostRegAllocPasses - This method may be implemented by targets that
- /// want to run passes after register allocation but before prolog-epilog
+ /// addPostRegAlloc - This method may be implemented by targets that want
+ /// to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
+
+ /// addPreSched2 - This method may be implemented by targets that want to
+ /// run passes after prolog-epilog insertion and before the second instruction
+ /// scheduling pass. This should return true if -print-machineinstrs should
+ /// print after these passes.
+ virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
+ return false;
+ }
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index a38d8cc..4e713a6 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -317,6 +317,10 @@
PM.add(createPrologEpilogCodeInserter());
printAndVerify(PM);
+ // Run pre-sched2 passes.
+ if (addPreSched2(PM, OptLevel))
+ printAndVerify(PM);
+
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None) {
PM.add(createPostRAScheduler());