commit 629adde69953fa53362d20ddb7b4e67ed78b8ae3
author Evan Cheng <evan.cheng@apple.com> Wed Sep 30 08:49:50 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Sep 30 08:49:50 2009 +0000
tree 7d283bc27041b900391bed9d9cdf37e3acbd94c2
parent 48af260bb1308a2a2cbd6642727465932e7cd0a7

Add a target hook to add pre- post-regalloc scheduling passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83144 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/LLVMTargetMachine.cpp

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index a38d8cc..4e713a6 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -317,6 +317,10 @@
   PM.add(createPrologEpilogCodeInserter());
   printAndVerify(PM);
 
+  // Run pre-sched2 passes.
+  if (addPreSched2(PM, OptLevel))
+    printAndVerify(PM);
+
   // Second pass scheduler.
   if (OptLevel != CodeGenOpt::None) {
     PM.add(createPostRAScheduler());