Move load / store multiple before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index ef42bd2..32ddc20 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -22,10 +22,6 @@
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
-static cl::opt<bool>
-LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
- cl::desc("Move ld / st multiple pass before postalloc scheduling"));
-
static const MCAsmInfo *createMCAsmInfo(const Target &T,
const StringRef &TT) {
Triple TheTriple(TT);
@@ -109,8 +105,7 @@
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
- if (LdStBeforeSched)
- PM.add(createARMLoadStoreOptimizationPass());
+ PM.add(createARMLoadStoreOptimizationPass());
return true;
}
@@ -118,11 +113,8 @@
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
- if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
- if (!LdStBeforeSched)
- PM.add(createARMLoadStoreOptimizationPass());
+ if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
- }
if (Subtarget.isThumb2()) {
PM.add(createThumb2ITBlockPass());