Don't use %g0 to materialize 0 directly.
The wired physreg doesn't work on tied operands like on MOVXCC.
Add a README note to fix this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index b4991fe..c831367 100644
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -57,3 +57,5 @@
* Fill delay slots
* Implement JIT support
+
+* Use %g0 directly to materialize 0. No instruction is required.
diff --git a/lib/Target/Sparc/SparcInstr64Bit.td b/lib/Target/Sparc/SparcInstr64Bit.td
index 3af494e..daafb43 100644
--- a/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/lib/Target/Sparc/SparcInstr64Bit.td
@@ -59,10 +59,6 @@
// preferable to use a constant pool load instead, depending on the
// microarchitecture.
-// The %g0 register is constant 0.
-// This is useful for stx %g0, [...], for example.
-def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>;
-
// Single-instruction patterns.
// The ALU instructions want their simm13 operands as i32 immediates.
diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index 37dcea9..dd6cee3 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -26,7 +26,7 @@
; restore %g0, %g0, %o0
;
; CHECK: ret_imm0
-; CHECK: or %g0, %g0, %i0
+; CHECK: or %g0, 0, %i0
define i64 @ret_imm0() {
ret i64 0
}
diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll
index 0c025b3..594eff6 100644
--- a/test/CodeGen/SPARC/64cond.ll
+++ b/test/CodeGen/SPARC/64cond.ll
@@ -98,3 +98,14 @@
%rv = select i1 %tobool, double %a, double %b
ret double %rv
}
+
+; The MOVXCC instruction can't use %g0 for its tied operand.
+; CHECK: select_consti64_xcc
+; CHECK: subcc
+; CHECK: movg %xcc, 123, %i0
+define i64 @select_consti64_xcc(i64 %x, i64 %y) {
+entry:
+ %tobool = icmp sgt i64 %x, %y
+ %rv = select i1 %tobool, i64 123, i64 0
+ ret i64 %rv
+}