commit 63b3d7113d93fda622c4954c6b1d046ce029044e
author Chris Lattner <sabre@nondot.org> Thu May 04 17:21:20 2006 +0000
committer Chris Lattner <sabre@nondot.org> Thu May 04 17:21:20 2006 +0000
tree a1e0a659d24e6615f29a8184a3ae0b23ef6e6e03
parent ceb408f6a263e319683209ae5c6f8d1e3e4d9b69

There shalt be only one "immediate" operand type!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Sparc/SparcAsmPrinter.cpp

diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index 2d81bbd..d95ca9c 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -153,8 +153,7 @@
       O << "%reg" << MO.getReg();
     break;
 
-  case MachineOperand::MO_SignExtendedImmed:
-  case MachineOperand::MO_UnextendedImmed:
+  case MachineOperand::MO_Immediate:
     O << (int)MO.getImmedValue();
     break;
   case MachineOperand::MO_MachineBasicBlock:
@@ -192,8 +191,7 @@
   if (OpTy == MachineOperand::MO_VirtualRegister &&
       MI->getOperand(opNum+1).getReg() == SP::G0)
     return;   // don't print "+%g0"
-  if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
-       OpTy == MachineOperand::MO_UnextendedImmed) &&
+  if (OpTy == MachineOperand::MO_Immediate &&
       MI->getOperand(opNum+1).getImmedValue() == 0)
     return;   // don't print "+0"