commit 63d66eed16a6ee4e838f2f7a4c8299def0722c20
author Evan Cheng <evan.cheng@apple.com> Tue Sep 28 23:50:49 2010 +0000
committer Evan Cheng <evan.cheng@apple.com> Tue Sep 28 23:50:49 2010 +0000
tree 8f6d45aaa9b70a0694825dabb532e81b91a6622d
parent e48155b25a40e0c1f285ab42b99b2503638d6c0d

Add support to model pipeline bypass / forwarding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCScheduleG5.td

diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td
index 2dffc48..1671f22 100644
--- a/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/lib/Target/PowerPC/PPCScheduleG5.td
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 def G5Itineraries : ProcessorItineraries<
-  [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [
+  [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [
   InstrItinData<IntGeneral  , [InstrStage<2, [IU1, IU2]>]>,
   InstrItinData<IntCompare  , [InstrStage<3, [IU1, IU2]>]>,
   InstrItinData<IntDivD     , [InstrStage<68, [IU1]>]>,