commit 643c040c9da38256a7405abf58e4da09964e83cb
author Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Wed May 27 17:23:44 2009 +0000
committer Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Wed May 27 17:23:44 2009 +0000
tree ea845becd986ec2cf30f812a4f65a6f02e9db78e
parent 70052f6a7de314581fb1600d3cf367aa6bd7f44a

Added support for fround, fextend and FP_TO_SINT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsInstrInfo.cpp

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 2ccbe89..6225fa9 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -55,7 +55,8 @@
   if (MI.getOpcode() == Mips::FMOV_S32 || 
       MI.getOpcode() == Mips::FMOV_D32 || 
       MI.getOpcode() == Mips::MFC1 || 
-      MI.getOpcode() == Mips::MTC1 ) {
+      MI.getOpcode() == Mips::MTC1 ||
+      MI.getOpcode() == Mips::MOVCCRToCCR) {
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
     return true;
@@ -69,6 +70,7 @@
       return true;
     }
   }
+
   return false;
 }
 
@@ -132,22 +134,23 @@
   if (I != MBB.end()) DL = I->getDebugLoc();
 
   if (DestRC != SrcRC) {
-    // Moves between coprocessors and cpu
+
+    // Copy to/from FCR31 condition register
     if ((DestRC == Mips::CPURegsRegisterClass) && 
+        (SrcRC == Mips::CCRRegisterClass))
+      BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
+    else if ((DestRC == Mips::CCRRegisterClass) && 
+        (SrcRC == Mips::CPURegsRegisterClass))
+      BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
+
+    // Moves between coprocessors and cpu
+    else if ((DestRC == Mips::CPURegsRegisterClass) && 
         (SrcRC == Mips::FGR32RegisterClass))
       BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
     else if ((DestRC == Mips::FGR32RegisterClass) &&
              (SrcRC == Mips::CPURegsRegisterClass))
       BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
 
-    // Condition registers
-    else if ((SrcRC == Mips::CCRRegisterClass) && 
-             (SrcReg == Mips::FCR31))
-      return true; // This register is used implicitly, no copy needed.
-    else if ((DestRC == Mips::CCRRegisterClass) && 
-             (DestReg == Mips::FCR31))
-      return true; // This register is used implicitly, no copy needed.
-
     // Move from/to Hi/Lo registers
     else if ((DestRC == Mips::HILORegisterClass) &&
              (SrcRC == Mips::CPURegsRegisterClass)) {
@@ -172,6 +175,8 @@
     BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
   else if (DestRC == Mips::AFGR64RegisterClass)
     BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
+  else if (DestRC == Mips::CCRRegisterClass)
+    BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
   else
     // Can't copy this register
     return false;