commit 6448d91ad1e5497fe2f7015d61b57cb5f3040879
author Dan Gohman <gohman@apple.com> Thu Sep 04 15:39:15 2008 +0000
committer Dan Gohman <gohman@apple.com> Thu Sep 04 15:39:15 2008 +0000
tree b2b0275f484bd3953e8b38c941fdff9eaddec82f
parent ef7803217a401e7be14ea26d70f12fb3ec7da66f

Clean up uses of TargetLowering::getTargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e414fdf..71afb27 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3452,7 +3452,7 @@
       TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
     LoadSDNode *LD = cast<LoadSDNode>(LD1);
     unsigned Align = LD->getAlignment();
-    unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
+    unsigned NewAlign = TLI.getTargetData()->
       getABITypeAlignment(VT.getTypeForMVT());
     if (NewAlign <= Align &&
         (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT)))
@@ -3507,7 +3507,7 @@
       !cast<LoadSDNode>(N0)->isVolatile() &&
       (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    unsigned Align = TLI.getTargetMachine().getTargetData()->
+    unsigned Align = TLI.getTargetData()->
       getABITypeAlignment(VT.getTypeForMVT());
     unsigned OrigAlign = LN0->getAlignment();
     if (Align <= OrigAlign) {
@@ -4611,7 +4611,7 @@
       ST->isUnindexed()) {
     unsigned Align = ST->getAlignment();
     MVT SVT = Value.getOperand(0).getValueType();
-    unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
+    unsigned OrigAlign = TLI.getTargetData()->
       getABITypeAlignment(SVT.getTypeForMVT());
     if (Align <= OrigAlign &&
         ((!AfterLegalize && !ST->isVolatile()) ||
@@ -4842,7 +4842,7 @@
     if (NewLoad) {
       // Check the resultant load doesn't need a higher alignment than the
       // original load.
-      unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
+      unsigned NewAlign = TLI.getTargetData()->
         getABITypeAlignment(LVT.getTypeForMVT());
       if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
         return SDValue();

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1bada5e..3626081 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -302,7 +302,7 @@
 }
 
 const TargetMachine &SelectionDAG::getTarget() const {
-  return TLI.getTargetMachine();
+  return MF->getTarget();
 }
 
 //===----------------------------------------------------------------------===//

lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index e962368..8a114f7 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -310,7 +310,7 @@
       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
         MVT VT = ValueVTs[vti];
         unsigned NumRegisters = TLI.getNumRegisters(VT);
-        const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
+        const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
         for (unsigned i = 0; i != NumRegisters; ++i)
           BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
         PHIReg += NumRegisters;