commit 6467dfa40dc6a64fc2d2ca32279727d4accb1bf8
author Andrew Lenharth <andrewl@lenharth.org> Sat Nov 12 19:06:28 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Sat Nov 12 19:06:28 2005 +0000
tree dac9682c53359adbbc8e63dd1a21b5b9b35d3919
parent 82a698ce6a37c25d1bc6aa451f4aa95566b028cd

fix more regressions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24335 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 0074fd4..1e6bab6 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -369,7 +369,7 @@
       //assert(0 && "Setcc On float?\n");
       std::cerr << "Setcc on float!\n";
       Tmp3 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1);
+      BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
       Tmp1 = Tmp3;
     }
   if (SetCC->getOperand(1).getValueType() == MVT::f32)
@@ -377,7 +377,7 @@
       //assert (0 && "Setcc On float?\n");
       std::cerr << "Setcc on float!\n";
       Tmp3 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2);
+      BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
       Tmp2 = Tmp3;
     }