commit 6510b22cec7de4f0acc9965ec24c3668a6a8a87e
author Nate Begeman <natebegeman@mac.com> Thu Dec 01 04:51:06 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Thu Dec 01 04:51:06 2005 +0000
tree 4fadf46880895213994813192581c17f61c3a00d
parent 5dfc55c304b051a33f4ee30a2e1b4bca85ddb75e

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index f250a7b..c1a7f47 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -1208,7 +1208,7 @@
         // Pick the register class of the right type that contains this physreg.
         for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
              E = MRI.regclass_end(); I != E; ++I)
-          if ((*I)->getType() == Node->getValueType(0) &&
+          if ((*I)->hasType(Node->getValueType(0)) &&
               (*I)->contains(SrcReg)) {
             TRC = *I;
             break;