Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 3f7d5db..c2fcf1a2 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -62,13 +62,21 @@
return Result; // No info for variable operand instrs.
for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
- if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
+ if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
Result.push_back(Inst.OperandList[i].Rec);
- else {
+ } else {
// This might be a multiple operand thing.
- // FIXME: Targets like X86 have registers in their multi-operand operands.
- for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
- Result.push_back(0);
+ // Targets like X86 have registers in their multi-operand operands.
+ DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+ unsigned NumDefs = MIOI->getNumArgs();
+ for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
+ if (NumDefs <= j) {
+ Result.push_back(0);
+ } else {
+ DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
+ Result.push_back(Def ? Def->getDef() : 0);
+ }
+ }
}
}
return Result;
@@ -124,7 +132,9 @@
N = ++OperandListNum;
OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
- if (Record *RC = OperandInfo[i]) {
+ Record *RC = OperandInfo[i];
+ // FIXME: We only care about register operands for now.
+ if (RC && RC->isSubClassOf("RegisterClass")) {
OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
} else {
OS << "{ 0 }, ";