constify accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h
index fd7431f..dede05f 100644
--- a/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -216,7 +216,8 @@
/// getRegClassVirtRegs - Return the list of virtual registers of the given
/// target register class.
- std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
+ const std::vector<unsigned> &
+ getRegClassVirtRegs(const TargetRegisterClass *RC) const {
return RegClass2VRegMap[RC->getID()];
}
diff --git a/lib/CodeGen/PreAllocSplitting.cpp b/lib/CodeGen/PreAllocSplitting.cpp
index eb19be1..997e82f 100644
--- a/lib/CodeGen/PreAllocSplitting.cpp
+++ b/lib/CodeGen/PreAllocSplitting.cpp
@@ -1154,7 +1154,7 @@
// codegen is not modelling. Ignore these barriers for now.
if (!TII->isSafeToMoveRegClassDefs(*RC))
continue;
- std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
+ const std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
unsigned Reg = VRs[i];
if (!LIs->hasInterval(Reg))