misched: Fix RegisterPressureTracker handling of DebugVals.
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169072 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index cc7aabd..0789a74 100644
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -603,7 +603,11 @@
SchedImpl->registerRoots();
+ // Advance past initial DebugValues.
+ assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
+ TopRPTracker.setPos(CurrentTop);
+
CurrentBottom = RegionEnd;
}
diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp
index 543c426..c7763dc 100644
--- a/lib/CodeGen/RegisterPressure.cpp
+++ b/lib/CodeGen/RegisterPressure.cpp
@@ -181,9 +181,6 @@
}
CurrPos = pos;
- while (CurrPos != MBB->end() && CurrPos->isDebugValue())
- ++CurrPos;
-
CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0);
if (RequireIntervals)
@@ -214,11 +211,20 @@
MachineBasicBlock::const_iterator());
}
+
+SlotIndex RegPressureTracker::getCurrSlot() const {
+ MachineBasicBlock::const_iterator IdxPos = CurrPos;
+ while (IdxPos != MBB->end() && IdxPos->isDebugValue())
+ ++IdxPos;
+ if (IdxPos == MBB->end())
+ return LIS->getMBBEndIdx(MBB);
+ return LIS->getInstructionIndex(IdxPos).getRegSlot();
+}
+
/// Set the boundary for the top of the region and summarize live ins.
void RegPressureTracker::closeTop() {
if (RequireIntervals)
- static_cast<IntervalPressure&>(P).TopIdx =
- LIS->getInstructionIndex(CurrPos).getRegSlot();
+ static_cast<IntervalPressure&>(P).TopIdx = getCurrSlot();
else
static_cast<RegionPressure&>(P).TopPos = CurrPos;
@@ -236,11 +242,7 @@
/// Set the boundary for the bottom of the region and summarize live outs.
void RegPressureTracker::closeBottom() {
if (RequireIntervals)
- if (CurrPos == MBB->end())
- static_cast<IntervalPressure&>(P).BottomIdx = LIS->getMBBEndIdx(MBB);
- else
- static_cast<IntervalPressure&>(P).BottomIdx =
- LIS->getInstructionIndex(CurrPos).getRegSlot();
+ static_cast<IntervalPressure&>(P).BottomIdx = getCurrSlot();
else
static_cast<RegionPressure&>(P).BottomPos = CurrPos;
@@ -510,7 +512,7 @@
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIdx = getCurrSlot();
// Open the bottom of the region using slot indexes.
if (isBottomClosed()) {
@@ -769,7 +771,7 @@
const LiveInterval *LI = &LIS->getInterval(Reg);
// FIXME: allow the caller to pass in the list of vreg uses that remain to
// be bottom-scheduled to avoid searching uses at each query.
- SlotIndex CurrIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIndex CurrIdx = getCurrSlot();
if (LI->killedAt(SlotIdx)
&& !findUseBetween(Reg, CurrIdx, SlotIdx, MRI, LIS)) {
decreaseVirtRegPressure(Reg);
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index fd75576..2a41293 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -713,17 +713,17 @@
addSchedBarrierDeps();
// Walk the list of instructions, from bottom moving up.
- MachineInstr *PrevMI = NULL;
+ MachineInstr *DbgMI = NULL;
for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
MII != MIE; --MII) {
MachineInstr *MI = prior(MII);
- if (MI && PrevMI) {
- DbgValues.push_back(std::make_pair(PrevMI, MI));
- PrevMI = NULL;
+ if (MI && DbgMI) {
+ DbgValues.push_back(std::make_pair(DbgMI, MI));
+ DbgMI = NULL;
}
if (MI->isDebugValue()) {
- PrevMI = MI;
+ DbgMI = MI;
continue;
}
if (RPTracker) {
@@ -917,8 +917,8 @@
}
}
}
- if (PrevMI)
- FirstDbgValue = PrevMI;
+ if (DbgMI)
+ FirstDbgValue = DbgMI;
Defs.clear();
Uses.clear();