commit 6596a6207627ed59f568883924a21e642934c083
author Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Thu Jul 01 01:20:06 2010 +0000
committer Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Thu Jul 01 01:20:06 2010 +0000
tree cb40352d745211c3eb2676194aea63065b64e546
parent 2e5238ffa0becb2d673bd993e59747ec5087bf80

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86MCCodeEmitter.cpp

diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp
index 80f56e1..9f36aaa 100644
--- a/lib/Target/X86/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/X86MCCodeEmitter.cpp
@@ -449,6 +449,9 @@
   if (TSFlags & X86II::OpSize)
     VEX_PP = 0x01;
 
+  if ((TSFlags >> 32) & X86II::VEX_W)
+    VEX_W = 1;
+
   switch (TSFlags & X86II::Op0Mask) {
   default: assert(0 && "Invalid prefix!");
   case X86II::T8:  // 0F 38
@@ -508,15 +511,20 @@
         VEX_X = 0x0;
     }
     break;
-  default: // MRM0r-MRM7r
+  default: // MRMDestReg, MRM0r-MRM7r
+    if (MI.getOperand(CurOp).isReg() &&
+        X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+      VEX_B = 0;
+
     if (HasVEX_4V)
       VEX_4V = getVEXRegisterEncoding(MI, CurOp);
 
     CurOp++;
     for (; CurOp != NumOps; ++CurOp) {
       const MCOperand &MO = MI.getOperand(CurOp);
-      if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
-        VEX_B = 0x0;
+      if (MO.isReg() && !HasVEX_4V &&
+          X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
+        VEX_R = 0x0;
     }
     break;
     assert(0 && "Not implemented!");
@@ -535,7 +543,7 @@
   //
   unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
 
-  if (VEX_B && VEX_X) { // 2 byte VEX prefix
+  if (VEX_B && VEX_X && !VEX_W) { // 2 byte VEX prefix
     EmitByte(0xC5, CurByte, OS);
     EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
     return;
@@ -543,7 +551,7 @@
 
   // 3 byte VEX prefix
   EmitByte(0xC4, CurByte, OS);
-  EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_5M, CurByte, OS);
+  EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
   EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
 }