Support added for ctlz intrinsic, test case added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54516 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index fb0cb63..00f8cdb 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -119,7 +119,6 @@
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
- setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTR, MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
@@ -147,6 +146,9 @@
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
+ if (!Subtarget->hasBitCount())
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+
setStackPointerRegisterToSaveRestore(Mips::SP);
computeRegisterProperties();
}
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index d4116c4..89e8ee2 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -51,7 +51,8 @@
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
-def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
+def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
+def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
@@ -332,15 +333,6 @@
!strconcat(instr_asm, "\t$src"),
[], IIHiLo>;
-// Count Leading Ones/Zeros in Word
-class CountLeading<bits<6> func, string instr_asm>:
- FR< 0x1c,
- func,
- (outs CPURegs:$dst),
- (ins CPURegs:$src),
- !strconcat(instr_asm, "\t$dst, $src"),
- [], IIAlu>;
-
class EffectiveAddress<string instr_asm> :
FI<0x09,
(outs CPURegs:$dst),
@@ -348,6 +340,13 @@
instr_asm,
[(set CPURegs:$dst, addr:$addr)], IIAlu>;
+// Count Leading Ones/Zeros in Word
+class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
+ FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
+ !strconcat(instr_asm, "\t$dst, $src"),
+ [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
+
+// Sign Extend in Register.
class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
!strconcat(instr_asm, "\t$dst, $src"),
@@ -494,6 +493,12 @@
def SEH : SignExtInReg<0x20, "seh", i16>;
}
+/// Count Leading
+let Predicates = [HasBitCount] in {
+ def CLZ : CountLeading<0b010110, "clz", ctlz>;
+//def CLO : CountLeading<0b010110, "clo">;
+}
+
/// No operation
let addr=0 in
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
@@ -504,13 +509,6 @@
// can be matched. It's similar to Sparc LEA_ADDRi
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
-// Count Leading
-// CLO/CLZ are part of the newer MIPS32(tm) instruction
-// set and not older Mips I keep this for future use
-// though.
-//def CLO : CountLeading<0x21, "clo">;
-//def CLZ : CountLeading<0x20, "clz">;
-
// MADD*/MSUB* are not part of MipsI either.
//def MADD : MArithR<0x00, "madd">;
//def MADDU : MArithR<0x01, "maddu">;
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index d8c0797..b1e1806 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -57,6 +57,7 @@
MipsArchVersion = Mips2;
HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
HasSEInReg = true;
+ HasBitCount = true;
}
// Abicall is the default for O32 ABI and is ignored