Convert asmprinter to new style of instruction printer
Start asmprintergen'ifying machine instrs with memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15646 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index f8c582f..a17d5d5 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -105,7 +105,8 @@
bool printInstruction(const MachineInstr *MI);
// This method is used by the tablegen'erated instruction printer.
- void printOperand(const MachineOperand &MO, MVT::ValueType VT) {
+ void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) {
+ const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_MachineRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
// Bug Workaround: See note in Printer::doInitialization about %.
@@ -115,6 +116,21 @@
}
}
+ void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+ MVT::ValueType VT) {
+ switch (VT) {
+ default: assert(0 && "Unknown arg size!");
+ case MVT::i8: O << "BYTE PTR "; break;
+ case MVT::i16: O << "WORD PTR "; break;
+ case MVT::i32:
+ case MVT::f32: O << "DWORD PTR "; break;
+ case MVT::i64:
+ case MVT::f64: O << "QWORD PTR "; break;
+ case MVT::f80: O << "XWORD PTR "; break;
+ }
+ printMemReference(MI, OpNo);
+ }
+
bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC);
void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);