Add support for a few simple fixups to the ARM Darwin asm backend. This allows
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 296a5c9..94fe8fc 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -234,7 +234,7 @@
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = ARM::PC; // Rn is PC.
+ Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm12 = 0;
assert(MO.isExpr() && "Unexpected machine operand type!");
@@ -246,9 +246,6 @@
} else
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
- if (Reg == ARM::PC)
- return ARM::PC << 13; // Rn is PC;
-
uint32_t Binary = Imm12 & 0xfff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (isAdd)
@@ -268,7 +265,7 @@
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = ARM::PC; // Rn is PC.
+ Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm8 = 0;
assert(MO.isExpr() && "Unexpected machine operand type!");
@@ -280,9 +277,6 @@
} else
EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
- if (Reg == ARM::PC)
- return ARM::PC << 9; // Rn is PC;
-
uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)