commit 68011700f9b857600cfc49da0ac64d833fb66ce2
author Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Wed Jul 09 04:45:36 2008 +0000
committer Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Wed Jul 09 04:45:36 2008 +0000
tree 15c41b5f8967962bf4f76caca28d7708a6c24c0b
parent ffed71b6ffdeba106b0b04b0142bf4f9ebd75fb7

Fixe typos and 80 column size problems

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsInstrInfo.cpp

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 403adec..687237f 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -289,7 +289,8 @@
   case Mips::FMOV_D32:
     if ((MI->getOperand(0).isRegister()) &&
         (MI->getOperand(1).isRegister())) {
-      const TargetRegisterClass *RC = RI.getRegClass(MI->getOperand(0).getReg());
+      const TargetRegisterClass 
+        *RC = RI.getRegClass(MI->getOperand(0).getReg());
       unsigned StoreOpc, LoadOpc;
 
       if (RC == Mips::FGR32RegisterClass) {