misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 09f2c5b..ed06672 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -160,8 +160,8 @@
MachineBasicBlock::iterator end,
unsigned endcount) {
BB = bb;
- Begin = begin;
- End = end;
+ RegionBegin = begin;
+ RegionEnd = end;
EndIndex = endcount;
// Check to see if the scheduler cares about latencies.
@@ -185,7 +185,7 @@
/// are too high to be hidden by the branch or when the liveout registers
/// used by instructions in the fallthrough block.
void ScheduleDAGInstrs::addSchedBarrierDeps() {
- MachineInstr *ExitMI = End != BB->end() ? &*End : 0;
+ MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
ExitSU.setInstr(ExitMI);
bool AllDepKnown = ExitMI &&
(ExitMI->isCall() || ExitMI->isBarrier());
@@ -477,7 +477,7 @@
// which is contained within a basic block.
SUnits.reserve(BB->size());
- for (MachineBasicBlock::iterator I = Begin; I != End; ++I) {
+ for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
MachineInstr *MI = I;
if (MI->isDebugValue())
continue;
@@ -535,7 +535,7 @@
// Walk the list of instructions, from bottom moving up.
MachineInstr *PrevMI = NULL;
- for (MachineBasicBlock::iterator MII = End, MIE = Begin;
+ for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
MII != MIE; --MII) {
MachineInstr *MI = prior(MII);
if (MI && PrevMI) {