commit 68bff8e15db12aa565818914cf7e452171f13e3a
author Alkis Evlogimenos <alkis@evlogimenos.com> Tue Feb 17 15:33:14 2004 +0000
committer Alkis Evlogimenos <alkis@evlogimenos.com> Tue Feb 17 15:33:14 2004 +0000
tree 2256df0e031b62e0b7c874c703363495eafa42e4
parent e287a0044073c94603466791194657aeba8f3501

Add OR and XOR memory operand support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11549 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/PeepholeOptimizer.cpp

diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index 3e0af70..4d52b74 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -156,6 +156,8 @@
   case X86::ADDmi16:  case X86::ADDmi32:
   case X86::SUBmi16:  case X86::SUBmi32:
   case X86::ANDmi16:  case X86::ANDmi32:
+  case X86::ORmi16:  case X86::ORmi32:
+  case X86::XORmi16:  case X86::XORmi32:
     assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
     if (MI->getOperand(4).isImmediate()) {
       int Val = MI->getOperand(4).getImmedValue();
@@ -170,6 +172,10 @@
         case X86::SUBmi32:  Opcode = X86::SUBmi32b; break;
         case X86::ANDmi16:  Opcode = X86::ANDmi16b; break;
         case X86::ANDmi32:  Opcode = X86::ANDmi32b; break;
+        case X86::ORmi16:   Opcode = X86::ORmi16b; break;
+        case X86::ORmi32:   Opcode = X86::ORmi32b; break;
+        case X86::XORmi16:  Opcode = X86::XORmi16b; break;
+        case X86::XORmi32:  Opcode = X86::XORmi32b; break;
         }
         unsigned R0 = MI->getOperand(0).getReg();
         unsigned Scale = MI->getOperand(1).getImmedValue();