Just use a single isMoveInstr to catch all the cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0b61d4e..c5e74bf 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -490,16 +490,21 @@
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
- unsigned oc = MI.getOpcode();
- if (oc == ARM::FCPYS ||
- oc == ARM::FCPYD ||
- oc == ARM::VMOVD ||
- oc == ARM::VMOVQ) {
+ switch (MI.getOpcode()) {
+ case ARM::FCPYS:
+ case ARM::FCPYD:
+ case ARM::VMOVD:
+ case ARM::VMOVQ: {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
}
- else if (oc == getOpcode(ARMII::MOVr)) {
+ case ARM::MOVr:
+ case ARM::tMOVr:
+ case ARM::tMOVgpr2tgpr:
+ case ARM::tMOVtgpr2gpr:
+ case ARM::tMOVgpr2gpr:
+ case ARM::t2MOVr: {
assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
@@ -508,6 +513,7 @@
DstReg = MI.getOperand(0).getReg();
return true;
}
+ }
return false;
}