Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 8553240..9623627 100644
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -396,8 +396,7 @@
 /// addLiveIn - Add the specified physical register as a live-in value and
 /// create a corresponding virtual register for it.
 unsigned MachineFunction::addLiveIn(unsigned PReg,
-                                    const TargetRegisterClass *RC,
-                                    DebugLoc DL) {
+                                    const TargetRegisterClass *RC) {
   MachineRegisterInfo &MRI = getRegInfo();
   unsigned VReg = MRI.getLiveInVirtReg(PReg);
   if (VReg) {
@@ -406,7 +405,6 @@
   }
   VReg = MRI.createVirtualRegister(RC);
   MRI.addLiveIn(PReg, VReg);
-  MRI.addLiveInLoc(VReg, DL);
   return VReg;
 }
 
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index b3fb337..7244d5f 100644
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -210,15 +210,8 @@
         LiveIns.erase(LiveIns.begin() + i);
         --i; --e;
       } else {
-        DebugLoc DL;
-        // If there is a location for this live in then use it.
-        DenseMap<unsigned, DebugLoc>::iterator DLI = 
-          LiveInLocs.find(LiveIns[i].second);
-        if (DLI != LiveInLocs.end())
-          DL = DLI->second;
-
         // Emit a copy.
-        BuildMI(*EntryMBB, EntryMBB->begin(), DL,
+        BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
           .addReg(LiveIns[i].first);
 
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index a1a70c3..8f466d9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -348,7 +348,7 @@
   SDValue getControlRoot();
 
   DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
-  void setCurDebugLoc(DebugLoc dl){ CurDebugLoc = dl; }
+
   unsigned getSDNodeOrder() const { return SDNodeOrder; }
 
   void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 62ebc81..ae63f2e 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -851,17 +851,8 @@
       PrepareEHLandingPad();
 
     // Lower any arguments needed in this block if this is the entry block.
-    if (LLVMBB == &Fn.getEntryBlock()) {
-      for (BasicBlock::const_iterator DBI = LLVMBB->begin(), DBE = LLVMBB->end();
-           DBI != DBE; ++DBI) {
-        if (const DbgInfoIntrinsic *DI = dyn_cast<DbgInfoIntrinsic>(DBI)) {
-          const DebugLoc DL = DI->getDebugLoc();
-          SDB->setCurDebugLoc(DL);
-          break;
-        }
-      }
+    if (LLVMBB == &Fn.getEntryBlock())
       LowerArguments(LLVMBB);
-    }
 
     // Before doing SelectionDAG ISel, see if FastISel has been requested.
     if (FastIS) {