Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21676 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 574f864..53d8a9e 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -76,6 +76,10 @@
setOperationAction(ISD::SREM , MVT::f32 , Expand);
setOperationAction(ISD::SREM , MVT::f64 , Expand);
+ // setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
+ // setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
+ // setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
+
//If this didn't legalize into a div....
// setOperationAction(ISD::SREM , MVT::i64, Expand);
// setOperationAction(ISD::UREM , MVT::i64, Expand);
@@ -1215,6 +1219,15 @@
Node->dump();
assert(0 && "Node not handled!\n");
+ case ISD::CTPOP:
+ case ISD::CTTZ:
+ case ISD::CTLZ:
+ Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
+ (opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+ return Result;
+
case ISD::MULHU:
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));