Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp
index 151c63e..8ab4d4b 100644
--- a/lib/CodeGen/BranchFolding.cpp
+++ b/lib/CodeGen/BranchFolding.cpp
@@ -346,14 +346,13 @@
/// EstimateRuntime - Make a rough estimate for how long it will take to run
/// the specified code.
static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
- MachineBasicBlock::iterator E,
- const TargetInstrInfo *TII) {
+ MachineBasicBlock::iterator E) {
unsigned Time = 0;
for (; I != E; ++I) {
- const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
- if (TID.Flags & M_CALL_FLAG)
+ const TargetInstrDescriptor *TID = I->getDesc();
+ if (TID->isCall())
Time += 10;
- else if (TID.isSimpleLoad() || (TID.Flags & M_MAY_STORE_FLAG))
+ else if (TID->isSimpleLoad() || TID->mayStore())
Time += 2;
else
++Time;
@@ -368,7 +367,6 @@
MachineBasicBlock::iterator MBB1I,
MachineBasicBlock *MBB2,
MachineBasicBlock::iterator MBB2I,
- const TargetInstrInfo *TII,
MachineBasicBlock *PredBB) {
// If one block is the entry block, split the other one; we can't generate
// a branch to the entry block, as its label is not emitted.
@@ -389,8 +387,8 @@
// TODO: if we had some notion of which block was hotter, we could split
// the hot block, so it is the fall-through. Since we don't have profile info
// make a decision based on which will hurt most to split.
- unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I, TII);
- unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I, TII);
+ unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I);
+ unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I);
// If the MBB1 prefix takes "less time" to run than the MBB2 prefix, split the
// MBB1 block so it falls through. This will penalize the MBB2 path, but will
@@ -544,7 +542,7 @@
}
// Decide whether we want to split CurMBB or MBB2.
- if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, TII, PredBB)) {
+ if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, PredBB)) {
CurMBB = SplitMBBAt(*CurMBB, BBI1);
BBI1 = CurMBB->begin();
MergePotentials.back().second = CurMBB;
@@ -766,8 +764,7 @@
/// a strict ordering, returning true for both (MBB1,MBB2) and (MBB2,MBB1) will
/// result in infinite loops.
static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
- MachineBasicBlock *MBB2,
- const TargetInstrInfo &TII) {
+ MachineBasicBlock *MBB2) {
// Right now, we use a simple heuristic. If MBB2 ends with a call, and
// MBB1 doesn't, we prefer to fall through into MBB1. This allows us to
// optimize branches that branch to either a return block or an assert block
@@ -781,7 +778,7 @@
MachineInstr *MBB1I = --MBB1->end();
MachineInstr *MBB2I = --MBB2->end();
- return TII.isCall(MBB2I->getOpcode()) && !TII.isCall(MBB1I->getOpcode());
+ return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
}
/// OptimizeBlock - Analyze and optimize control flow related to the specified
@@ -894,7 +891,7 @@
// last. Only do the swap if one is clearly better to fall through than
// the other.
if (FallThrough == --MBB->getParent()->end() &&
- !IsBetterFallthrough(PriorTBB, MBB, *TII))
+ !IsBetterFallthrough(PriorTBB, MBB))
DoTransform = false;
// We don't want to do this transformation if we have control flow like:
@@ -961,7 +958,7 @@
// If this branch is the only thing in its block, see if we can forward
// other blocks across it.
if (CurTBB && CurCond.empty() && CurFBB == 0 &&
- TII->isBranch(MBB->begin()->getOpcode()) && CurTBB != MBB) {
+ MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
// This block may contain just an unconditional branch. Because there can
// be 'non-branch terminators' in the block, try removing the branch and
// then seeing if the block is empty.
diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp
index 550b52b..36e3fed 100644
--- a/lib/CodeGen/Collector.cpp
+++ b/lib/CodeGen/Collector.cpp
@@ -359,7 +359,7 @@
BBE = MF.end(); BBI != BBE; ++BBI)
for (MachineBasicBlock::iterator MI = BBI->begin(),
ME = BBI->end(); MI != ME; ++MI)
- if (TII->isCall(MI->getOpcode()))
+ if (MI->getDesc()->isCall())
VisitCallPoint(*MI);
}
diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp
index 17373fe..0fb7176 100644
--- a/lib/CodeGen/DwarfWriter.cpp
+++ b/lib/CodeGen/DwarfWriter.cpp
@@ -3147,15 +3147,13 @@
// Whether the last callsite entry was for an invoke.
bool PreviousIsInvoke = false;
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
-
// Visit all instructions in order of address.
for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (MI->getOpcode() != TargetInstrInfo::LABEL) {
- SawPotentiallyThrowing |= TII->isCall(MI->getOpcode());
+ SawPotentiallyThrowing |= MI->getDesc()->isCall();
continue;
}
diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp
index 54069c6..19ed70d 100644
--- a/lib/CodeGen/IfConversion.cpp
+++ b/lib/CodeGen/IfConversion.cpp
@@ -462,8 +462,7 @@
MachineBasicBlock::iterator I = BB->end();
while (I != BB->begin()) {
--I;
- const TargetInstrDescriptor *TID = I->getInstrDescriptor();
- if ((TID->Flags & M_BRANCH_FLAG) == 0)
+ if (!I->getDesc()->isBranch())
break;
}
return I;
@@ -522,7 +521,7 @@
/// ScanInstructions - Scan all the instructions in the block to determine if
/// the block is predicable. In most cases, that means all the instructions
-/// in the block has M_PREDICABLE flag. Also checks if the block contains any
+/// in the block are isPredicable(). Also checks if the block contains any
/// instruction which can clobber a predicate (e.g. condition code register).
/// If so, the block is not predicable unless it's the last instruction.
void IfConverter::ScanInstructions(BBInfo &BBI) {
@@ -551,13 +550,12 @@
bool SeenCondBr = false;
for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
I != E; ++I) {
- const TargetInstrDescriptor *TID = I->getInstrDescriptor();
- if ((TID->Flags & M_NOT_DUPLICABLE) != 0)
+ const TargetInstrDescriptor *TID = I->getDesc();
+ if (TID->isNotDuplicable())
BBI.CannotBeCopied = true;
bool isPredicated = TII->isPredicated(I);
- bool isCondBr = BBI.IsBrAnalyzable &&
- (TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0;
+ bool isCondBr = BBI.IsBrAnalyzable && TID->isBranch() && !TID->isBarrier();
if (!isCondBr) {
if (!isPredicated)
@@ -594,7 +592,7 @@
if (TII->DefinesPredicate(I, PredDefs))
BBI.ClobbersPred = true;
- if ((TID->Flags & M_PREDICABLE) == 0) {
+ if (!TID->isPredicable()) {
BBI.IsUnpredicable = true;
return;
}
@@ -1136,10 +1134,10 @@
bool IgnoreBr) {
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
E = FromBBI.BB->end(); I != E; ++I) {
- const TargetInstrDescriptor *TID = I->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = I->getDesc();
bool isPredicated = TII->isPredicated(I);
// Do not copy the end of the block branches.
- if (IgnoreBr && !isPredicated && (TID->Flags & M_BRANCH_FLAG) != 0)
+ if (IgnoreBr && !isPredicated && TID->isBranch())
break;
MachineInstr *MI = I->clone();
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 6f74774..6701e5b 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -615,7 +615,7 @@
return false;
isLoad = false;
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
tii_->isTriviallyReMaterializable(MI)) {
isLoad = TID->isSimpleLoad();
@@ -680,7 +680,7 @@
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
unsigned MRInfo = 0;
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
// If it is an implicit def instruction, just delete it.
if (TID->Flags & M_IMPLICIT_DEF_FLAG) {
RemoveMachineInstrFromMaps(MI);
@@ -1226,7 +1226,7 @@
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->isSimpleLoad()));
+ (DefIsReMat && (ReMatDefMI->getDesc()->isSimpleLoad()));
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
@@ -1308,7 +1308,7 @@
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && ReMatDefMI->getInstrDescriptor()->isSimpleLoad());
+ (DefIsReMat && ReMatDefMI->getDesc()->isSimpleLoad());
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
@@ -1423,7 +1423,7 @@
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
- if (isLoadSS || ReMatDefMI->getInstrDescriptor()->isSimpleLoad())
+ if (isLoadSS || ReMatDefMI->getDesc()->isSimpleLoad())
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
}
@@ -1451,8 +1451,8 @@
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
assert(UseIdx != -1);
- if (LastUse->getInstrDescriptor()->
- getOperandConstraint(UseIdx, TOI::TIED_TO) == -1) {
+ if (LastUse->getDesc()->getOperandConstraint(UseIdx, TOI::TIED_TO) ==
+ -1) {
LastUse->getOperand(UseIdx).setIsKill();
vrm.addKillPoint(LI->reg, LastUseIdx);
}
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index 7f93185..d2dcd38 100644
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -131,11 +131,10 @@
}
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
- const TargetInstrInfo& TII = *getParent()->getTarget().getInstrInfo();
iterator I = end();
- while (I != begin() && TII.isTerminatorInstr((--I)->getOpcode()))
+ while (I != begin() && (--I)->getDesc()->isTerminator())
; /*noop */
- if (I != end() && !TII.isTerminatorInstr(I->getOpcode())) ++I;
+ if (I != end() && !I->getDesc()->isTerminator()) ++I;
return I;
}
@@ -262,7 +261,7 @@
MachineBasicBlock::iterator I = end();
while (I != begin()) {
--I;
- if (!(I->getInstrDescriptor()->Flags & M_TERMINATOR_FLAG)) break;
+ if (!I->getDesc()->isTerminator()) break;
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 00be1f1..40ab4c2 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -288,7 +288,7 @@
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(const MachineInstr &MI) {
- TID = MI.getInstrDescriptor();
+ TID = MI.getDesc();
NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
@@ -538,8 +538,8 @@
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int MachineInstr::findFirstPredOperandIdx() const {
- const TargetInstrDescriptor *TID = getInstrDescriptor();
- if (TID->Flags & M_PREDICABLE) {
+ const TargetInstrDescriptor *TID = getDesc();
+ if (TID->isPredicable()) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
return i;
@@ -551,7 +551,7 @@
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
/// to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
- const TargetInstrDescriptor *TID = getInstrDescriptor();
+ const TargetInstrDescriptor *TID = getDesc();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO1 = getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
@@ -588,8 +588,8 @@
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
- if (TID->Flags & M_PREDICABLE) {
+ const TargetInstrDescriptor *TID = MI->getDesc();
+ if (TID->isPredicable()) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
// Predicated operands must be last operands.
@@ -612,7 +612,7 @@
++StartOp; // Don't print this operand again!
}
- OS << getInstrDescriptor()->Name;
+ OS << getDesc()->Name;
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
if (i != StartOp)
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index 94e1061..4c7ae48 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -225,23 +225,21 @@
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
DEBUG({
DOUT << "--- Checking if we can hoist " << I;
- if (I.getInstrDescriptor()->ImplicitUses) {
+ if (I.getDesc()->ImplicitUses) {
DOUT << " * Instruction has implicit uses:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
- const unsigned *ImpUses = I.getInstrDescriptor()->ImplicitUses;
-
- for (; *ImpUses; ++ImpUses)
+ for (const unsigned *ImpUses = I.getDesc()->ImplicitUses;
+ *ImpUses; ++ImpUses)
DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
}
- if (I.getInstrDescriptor()->ImplicitDefs) {
+ if (I.getDesc()->ImplicitDefs) {
DOUT << " * Instruction has implicit defines:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
- const unsigned *ImpDefs = I.getInstrDescriptor()->ImplicitDefs;
-
- for (; *ImpDefs; ++ImpDefs)
+ for (const unsigned *ImpDefs = I.getDesc()->ImplicitDefs;
+ *ImpDefs; ++ImpDefs)
DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
}
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 1d8f3ef..d7c0a7b 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -269,7 +269,7 @@
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = I;
- while (I2 != MBB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
+ while (I2 != MBB->begin() && (--I2)->getDesc()->isTerminator())
I = I2;
bool AtStart = I == MBB->begin();
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 7ea9623..3382823 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -173,8 +173,7 @@
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
- unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const TargetInstrDescriptor &Desc = *MI->getDesc();
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
@@ -204,7 +203,7 @@
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
+ int TiedOp = MI->getDesc()->findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 9e917bd..758c6c1 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -95,7 +95,7 @@
// Reaching a terminator instruction. Restore a scavenged register (which
// must be life out.
- if (TII->isTerminatorInstr(MI->getOpcode()))
+ if (MI->getDesc()->isTerminator())
restoreScavengedReg();
// Process uses first.
@@ -122,7 +122,7 @@
setUnused(ChangedRegs);
// Process defs.
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
@@ -152,7 +152,7 @@
MachineInstr *MI = MBBI;
// Process defs first.
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 1a5387b..3ef907e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -433,7 +433,7 @@
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
bool isOptDef = (IIOpNum < TID->numOperands)
? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 18cc303..207f371 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -35,8 +35,8 @@
bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const {
bool MadeChange = false;
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
- if (TID->Flags & M_PREDICABLE) {
+ const TargetInstrDescriptor *TID = MI->getDesc();
+ if (TID->isPredicable()) {
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
MachineOperand &MO = MI->getOperand(i);
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 8f0c473..9eb3d7a 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -93,7 +93,7 @@
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ++mi) {
- const TargetInstrDescriptor *TID = mi->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = mi->getDesc();
bool FirstTied = true;
for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 4ab2938..967e292 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -537,7 +537,7 @@
/// over.
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
std::vector<MachineOperand*> &KillOps) {
- const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI.getDesc();
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || !MO.isUse())
@@ -966,7 +966,7 @@
NextMII = next(MII);
MachineInstr &MI = *MII;
- const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI.getDesc();
// Insert restores here if asked to.
if (VRM.isRestorePt(&MI)) {
@@ -1436,7 +1436,7 @@
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
unsigned PhysReg;
- int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
+ int TiedOp = MI.getDesc()->findTiedToSrcOperand(i);
if (TiedOp != -1) {
PhysReg = MI.getOperand(TiedOp).getReg();
if (SubIdx) {