Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index b856715..62d4da4 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -201,8 +201,8 @@
}
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
- const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
- const unsigned opcode = MI.getOpcode();
+ const TargetInstrDescriptor *Desc = MI.getDesc();
+ unsigned opcode = Desc->Opcode;
// initial instruction mask
unsigned Value = 0xE0000000;
unsigned op;
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index cbf6ed2..5f54e1f 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -371,7 +371,7 @@
MBBSize += ARM::GetInstSize(I);
int Opc = I->getOpcode();
- if (TII->isBranch(Opc)) {
+ if (I->getDesc()->isBranch()) {
bool isCond = false;
unsigned Bits = 0;
unsigned Scale = 1;
@@ -423,7 +423,7 @@
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
- unsigned TSFlags = I->getInstrDescriptor()->TSFlags;
+ unsigned TSFlags = I->getDesc()->TSFlags;
switch (TSFlags & ARMII::AddrModeMask) {
default:
// Constant pool entries can reach anything.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index f40be58..3522637 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getInstrDescriptor()->numOperands >= 2 &&
+ assert(MI.getDesc()->numOperands >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
@@ -180,7 +180,7 @@
return NULL;
MachineInstr *MI = MBBI;
- unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
+ unsigned TSFlags = MI->getDesc()->TSFlags;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
@@ -200,7 +200,7 @@
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
unsigned NumOps = TID->numOperands;
bool isLoad = TID->isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
@@ -837,7 +837,7 @@
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
return false;
@@ -870,7 +870,7 @@
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MI->getDesc();
unsigned TSFlags = TID->TSFlags;
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
@@ -899,7 +899,7 @@
// jumptable. The size is 4 + 4 * number of entries.
unsigned NumOps = TID->numOperands;
MachineOperand JTOP =
- MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
+ MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index d522613..152e2d1 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -599,7 +599,7 @@
unsigned Base = MBBI->getOperand(1).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
- const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
+ const TargetInstrDescriptor *TID = MBBI->getDesc();
unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 82aa74e..fc72132 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -581,7 +581,7 @@
}
unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor();
+ const TargetInstrDescriptor &Desc = *MI.getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
@@ -797,7 +797,7 @@
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
else // tLDR has an extra register operand.
MI.addOperand(MachineOperand::CreateReg(0, false));
- } else if (TII.mayStore(Opcode)) {
+ } else if (Desc.mayStore()) {
// FIXME! This is horrific!!! We need register scavenging.
// Our temporary workaround has marked r3 unavailable. Of course, r3 is
// also a ABI register so it's possible that is is the register that is