diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index b856715..62d4da4 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -201,8 +201,8 @@
 }
 
 unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
-  const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
-  const unsigned opcode = MI.getOpcode();
+  const TargetInstrDescriptor *Desc = MI.getDesc();
+  unsigned opcode = Desc->Opcode;
   // initial instruction mask
   unsigned Value = 0xE0000000;
   unsigned op;
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index cbf6ed2..5f54e1f 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -371,7 +371,7 @@
       MBBSize += ARM::GetInstSize(I);
 
       int Opc = I->getOpcode();
-      if (TII->isBranch(Opc)) {
+      if (I->getDesc()->isBranch()) {
         bool isCond = false;
         unsigned Bits = 0;
         unsigned Scale = 1;
@@ -423,7 +423,7 @@
           // Basic size info comes from the TSFlags field.
           unsigned Bits = 0;
           unsigned Scale = 1;
-          unsigned TSFlags = I->getInstrDescriptor()->TSFlags;
+          unsigned TSFlags = I->getDesc()->TSFlags;
           switch (TSFlags & ARMII::AddrModeMask) {
           default: 
             // Constant pool entries can reach anything.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index f40be58..3522637 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
     return true;
   case ARM::MOVr:
   case ARM::tMOVr:
-    assert(MI.getInstrDescriptor()->numOperands >= 2 &&
+    assert(MI.getDesc()->numOperands >= 2 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            "Invalid ARM MOV instruction");
@@ -180,7 +180,7 @@
     return NULL;
 
   MachineInstr *MI = MBBI;
-  unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
+  unsigned TSFlags = MI->getDesc()->TSFlags;
   bool isPre = false;
   switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
   default: return NULL;
@@ -200,7 +200,7 @@
   MachineInstr *UpdateMI = NULL;
   MachineInstr *MemMI = NULL;
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  const TargetInstrDescriptor *TID = MI->getDesc();
   unsigned NumOps = TID->numOperands;
   bool isLoad = TID->isSimpleLoad();
   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
@@ -837,7 +837,7 @@
 
 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
                                     std::vector<MachineOperand> &Pred) const {
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  const TargetInstrDescriptor *TID = MI->getDesc();
   if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
     return false;
 
@@ -870,7 +870,7 @@
   const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
 
   // Basic size info comes from the TSFlags field.
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  const TargetInstrDescriptor *TID = MI->getDesc();
   unsigned TSFlags = TID->TSFlags;
   
   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
@@ -899,7 +899,7 @@
       // jumptable. The size is 4 + 4 * number of entries.
       unsigned NumOps = TID->numOperands;
       MachineOperand JTOP =
-        MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
+        MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
       unsigned JTI = JTOP.getIndex();
       MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
       const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index d522613..152e2d1 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -599,7 +599,7 @@
       unsigned Base = MBBI->getOperand(1).getReg();
       unsigned PredReg = 0;
       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
-      const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
+      const TargetInstrDescriptor *TID = MBBI->getDesc();
       unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 82aa74e..fc72132 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -581,7 +581,7 @@
   }
 
   unsigned Opcode = MI.getOpcode();
-  const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor();
+  const TargetInstrDescriptor &Desc = *MI.getDesc();
   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
   bool isSub = false;
 
@@ -797,7 +797,7 @@
         MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
       else  // tLDR has an extra register operand.
         MI.addOperand(MachineOperand::CreateReg(0, false));
-    } else if (TII.mayStore(Opcode)) {
+    } else if (Desc.mayStore()) {
       // FIXME! This is horrific!!! We need register scavenging.
       // Our temporary workaround has marked r3 unavailable. Of course, r3 is
       // also a ABI register so it's possible that is is the register that is
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 9a3f2ff..c3f92f8 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -59,7 +59,7 @@
 {
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (TII->hasDelaySlot(I->getOpcode())) {
+    if (I->getDesc()->hasDelaySlot()) {
       MachineBasicBlock::iterator J = I;
       ++J;
       BuildMI(MBB, J, TII->get(Mips::NOP));
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 130bfb8..cda5052 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -175,7 +175,7 @@
   // If there is only one terminator instruction, process it.
   unsigned LastOpc = LastInst->getOpcode();
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
-    if (!isBranch(LastInst->getOpcode()))
+    if (!LastInst->getDesc()->isBranch())
       return true;
 
     // Unconditional branch
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 2c5e3fc..87c698b 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -256,7 +256,8 @@
   // MTVRSAVE UpdatedVRSAVE
   MachineBasicBlock::iterator IP = EntryBB.begin();  // Insert Point
   BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
-  BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
+  BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
+          UpdatedVRSAVE).addReg(InVRSAVE);
   BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
   
   // Find all return blocks, outputting a restore in each epilog.
@@ -267,7 +268,7 @@
       // Skip over all terminator instructions, which are part of the return
       // sequence.
       MachineBasicBlock::iterator I2 = IP;
-      while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
+      while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
         IP = I2;
       
       // Emit: MTVRSAVE InVRSave
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index e041bda..00d14f2 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -65,7 +65,7 @@
 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (TII->hasDelaySlot(I->getOpcode())) {
+    if (I->getDesc()->hasDelaySlot()) {
       MachineBasicBlock::iterator J = I;
       ++J;
       BuildMI(MBB, J, TII->get(SP::NOP));
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index d8d1578..ba56caa 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -38,14 +38,13 @@
 }
 
 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  if (TID->Flags & M_TERMINATOR_FLAG) {
-    // Conditional branch is a special case.
-    if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
-      return true;
-    if ((TID->Flags & M_PREDICABLE) == 0)
-      return true;
-    return !isPredicated(MI);
-  }
-  return false;
+  const TargetInstrDescriptor *TID = MI->getDesc();
+  if (!TID->isTerminator()) return false;
+  
+  // Conditional branch is a special case.
+  if (TID->isBranch() && !TID->isBarrier())
+    return true;
+  if (!TID->isPredicable())
+    return true;
+  return !isPredicated(MI);
 }
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index bc2c007..3c67d62 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -115,7 +115,7 @@
       MCE.StartMachineBasicBlock(MBB);
       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
            I != E; ++I) {
-        const TargetInstrDescriptor *Desc = I->getInstrDescriptor();
+        const TargetInstrDescriptor *Desc = I->getDesc();
         emitInstruction(*I, Desc);
         // MOVPC32r is basically a call plus a pop instruction.
         if (Desc->Opcode == X86::MOVPC32r)
@@ -436,7 +436,7 @@
 /// size, and 3) use of X86-64 extended registers.
 unsigned Emitter::determineREX(const MachineInstr &MI) {
   unsigned REX = 0;
-  const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
+  const TargetInstrDescriptor *Desc = MI.getDesc();
 
   // Pseudo instructions do not need REX prefix byte.
   if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 354804c..8c5d569 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -205,7 +205,7 @@
 
   for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
     MachineInstr *MI = I;
-    unsigned Flags = MI->getInstrDescriptor()->TSFlags;
+    unsigned Flags = MI->getDesc()->TSFlags;
     if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
       continue;  // Efficiently ignore non-fp insts!
 
@@ -597,7 +597,7 @@
 ///
 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getInstrDescriptor()->numOperands;
+  unsigned NumOps = MI->getDesc()->numOperands;
   assert((NumOps == 5 || NumOps == 1) &&
          "Can only handle fst* & ftst instructions!");
 
@@ -657,7 +657,7 @@
 ///
 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getInstrDescriptor()->numOperands;
+  unsigned NumOps = MI->getDesc()->numOperands;
   assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
 
   // Is this the last use of the source register?
@@ -766,7 +766,7 @@
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
+  unsigned NumOperands = MI->getDesc()->numOperands;
   assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
   unsigned Dest = getFPReg(MI->getOperand(0));
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@@ -864,7 +864,7 @@
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
+  unsigned NumOperands = MI->getDesc()->numOperands;
   assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 42b25a9..ea49b42 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1243,16 +1243,15 @@
 }
 
 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  if (TID->Flags & M_TERMINATOR_FLAG) {
-    // Conditional branch is a special case.
-    if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
-      return true;
-    if ((TID->Flags & M_PREDICABLE) == 0)
-      return true;
-    return !isPredicated(MI);
-  }
-  return false;
+  const TargetInstrDescriptor *TID = MI->getDesc();
+  if (!TID->isTerminator()) return false;
+  
+  // Conditional branch is a special case.
+  if (TID->isBranch() && !TID->isBarrier())
+    return true;
+  if (!TID->isPredicable())
+    return true;
+  return !isPredicated(MI);
 }
 
 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
@@ -1277,7 +1276,7 @@
   
   // If there is only one terminator instruction, process it.
   if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
-    if (!isBranch(LastInst->getOpcode()))
+    if (!LastInst->getDesc()->isBranch())
       return true;
     
     // If the block ends with a branch there are 3 possibilities:
@@ -1695,7 +1694,7 @@
   bool isTwoAddrFold = false;
   unsigned NumOps = getNumOperands(MI->getOpcode());
   bool isTwoAddr = NumOps > 1 &&
-    MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+    MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
 
   MachineInstr *NewMI = NULL;
   // Folding a memory location into the two-address part of a two-address
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 34a860c..1e54417 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -139,68 +139,6 @@
   }
 }
 
-static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
-                                                     MachineOperand &MO) {
-  if (MO.isRegister())
-    MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
-                     false, false, MO.getSubReg());
-  else if (MO.isImmediate())
-    MIB = MIB.addImm(MO.getImm());
-  else if (MO.isFrameIndex())
-    MIB = MIB.addFrameIndex(MO.getIndex());
-  else if (MO.isGlobalAddress())
-    MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
-  else if (MO.isConstantPoolIndex())
-    MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
-  else if (MO.isJumpTableIndex())
-    MIB = MIB.addJumpTableIndex(MO.getIndex());
-  else if (MO.isExternalSymbol())
-    MIB = MIB.addExternalSymbol(MO.getSymbolName());
-  else
-    assert(0 && "Unknown operand for X86InstrAddOperand!");
-
-  return MIB;
-}
-
-static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
-                                  unsigned StackAlign) {
-  unsigned Opc = 0;
-  if (RC == &X86::GR64RegClass) {
-    Opc = X86::MOV64mr;
-  } else if (RC == &X86::GR32RegClass) {
-    Opc = X86::MOV32mr;
-  } else if (RC == &X86::GR16RegClass) {
-    Opc = X86::MOV16mr;
-  } else if (RC == &X86::GR8RegClass) {
-    Opc = X86::MOV8mr;
-  } else if (RC == &X86::GR32_RegClass) {
-    Opc = X86::MOV32_mr;
-  } else if (RC == &X86::GR16_RegClass) {
-    Opc = X86::MOV16_mr;
-  } else if (RC == &X86::RFP80RegClass) {
-    Opc = X86::ST_FpP80m;   // pops
-  } else if (RC == &X86::RFP64RegClass) {
-    Opc = X86::ST_Fp64m;
-  } else if (RC == &X86::RFP32RegClass) {
-    Opc = X86::ST_Fp32m;
-  } else if (RC == &X86::FR32RegClass) {
-    Opc = X86::MOVSSmr;
-  } else if (RC == &X86::FR64RegClass) {
-    Opc = X86::MOVSDmr;
-  } else if (RC == &X86::VR128RegClass) {
-    // FIXME: Use movaps once we are capable of selectively
-    // aligning functions that spill SSE registers on 16-byte boundaries.
-    Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
-  } else if (RC == &X86::VR64RegClass) {
-    Opc = X86::MMX_MOVQ64mr;
-  } else {
-    assert(0 && "Unknown regclass");
-    abort();
-  }
-
-  return Opc;
-}
-
 const TargetRegisterClass *
 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   if (RC == &X86::CCRRegClass)
@@ -790,7 +728,8 @@
   while (MBBI != MBB.begin()) {
     MachineBasicBlock::iterator PI = prior(MBBI);
     unsigned Opc = PI->getOpcode();
-    if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
+    if (Opc != X86::POP32r && Opc != X86::POP64r &&
+        !PI->getDesc()->isTerminator())
       break;
     --MBBI;
   }