diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 6faa972..cddeddd 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -17,12 +17,13 @@
 #include "SparcV8GenInstrInfo.inc"
 using namespace llvm;
 
-SparcV8InstrInfo::SparcV8InstrInfo()
-  : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
+SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST)
+  : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])),
+    RI(ST) {
 }
 
-static bool isZeroImmed (const MachineOperand &op) {
-  return (op.isImmediate() && op.getImmedValue() == 0);
+static bool isZeroImm(const MachineOperand &op) {
+  return op.isImmediate() && op.getImmedValue() == 0;
 }
 
 /// Return true if the instruction is a register to register move and
@@ -44,13 +45,13 @@
       SrcReg = MI.getOperand(1).getReg();
       return true;
     }
-  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
-    if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
-      DstReg = MI.getOperand(0).getReg();
-      SrcReg = MI.getOperand(1).getReg();
-      return true;
-    }
-  } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
+  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri &&
+             isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
+    DstReg = MI.getOperand(0).getReg();
+    SrcReg = MI.getOperand(1).getReg();
+    return true;
+  } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD ||
+             MI.getOpcode() == V8::FMOVD) {
     SrcReg = MI.getOperand(1).getReg();
     DstReg = MI.getOperand(0).getReg();
     return true;
diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h
index 067fb91..0b2ee90 100644
--- a/lib/Target/Sparc/SparcInstrInfo.h
+++ b/lib/Target/Sparc/SparcInstrInfo.h
@@ -34,7 +34,7 @@
 class SparcV8InstrInfo : public TargetInstrInfo {
   const SparcV8RegisterInfo RI;
 public:
-  SparcV8InstrInfo();
+  SparcV8InstrInfo(SparcV8Subtarget &ST);
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index dc7979f..abbf11f 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -13,6 +13,7 @@
 
 #include "SparcV8.h"
 #include "SparcV8RegisterInfo.h"
+#include "SparcV8Subtarget.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
@@ -21,9 +22,10 @@
 #include <iostream>
 using namespace llvm;
 
-SparcV8RegisterInfo::SparcV8RegisterInfo()
+SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
   : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
-                           V8::ADJCALLSTACKUP) {}
+                           V8::ADJCALLSTACKUP), Subtarget(st) {
+}
 
 void SparcV8RegisterInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
@@ -63,7 +65,8 @@
   else if (RC == V8::FPRegsRegisterClass)
     BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
   else if (RC == V8::DFPRegsRegisterClass)
-    BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg);
+    BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
+            1, DestReg).addReg(SrcReg);
   else
     assert (0 && "Can't copy this register");
 }
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 784a8e5..f739551 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -19,10 +19,13 @@
 
 namespace llvm {
 
+class SparcV8Subtarget;
 class Type;
 
 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
-  SparcV8RegisterInfo();
+  SparcV8Subtarget &Subtarget;
+  
+  SparcV8RegisterInfo(SparcV8Subtarget &st);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 88f88f4..d868c10 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -35,7 +35,7 @@
                                            IntrinsicLowering *IL,
                                            const std::string &FS)
   : TargetMachine("SparcV8", IL, false, 4, 4),
-    Subtarget(M, FS),
+    Subtarget(M, FS), InstrInfo(Subtarget),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
 }
 
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.cpp b/lib/Target/SparcV8/SparcV8InstrInfo.cpp
index 6faa972..cddeddd 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.cpp
@@ -17,12 +17,13 @@
 #include "SparcV8GenInstrInfo.inc"
 using namespace llvm;
 
-SparcV8InstrInfo::SparcV8InstrInfo()
-  : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
+SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST)
+  : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])),
+    RI(ST) {
 }
 
-static bool isZeroImmed (const MachineOperand &op) {
-  return (op.isImmediate() && op.getImmedValue() == 0);
+static bool isZeroImm(const MachineOperand &op) {
+  return op.isImmediate() && op.getImmedValue() == 0;
 }
 
 /// Return true if the instruction is a register to register move and
@@ -44,13 +45,13 @@
       SrcReg = MI.getOperand(1).getReg();
       return true;
     }
-  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
-    if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
-      DstReg = MI.getOperand(0).getReg();
-      SrcReg = MI.getOperand(1).getReg();
-      return true;
-    }
-  } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
+  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri &&
+             isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
+    DstReg = MI.getOperand(0).getReg();
+    SrcReg = MI.getOperand(1).getReg();
+    return true;
+  } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD ||
+             MI.getOpcode() == V8::FMOVD) {
     SrcReg = MI.getOperand(1).getReg();
     DstReg = MI.getOperand(0).getReg();
     return true;
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.h b/lib/Target/SparcV8/SparcV8InstrInfo.h
index 067fb91..0b2ee90 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.h
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.h
@@ -34,7 +34,7 @@
 class SparcV8InstrInfo : public TargetInstrInfo {
   const SparcV8RegisterInfo RI;
 public:
-  SparcV8InstrInfo();
+  SparcV8InstrInfo(SparcV8Subtarget &ST);
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index dc7979f..abbf11f 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -13,6 +13,7 @@
 
 #include "SparcV8.h"
 #include "SparcV8RegisterInfo.h"
+#include "SparcV8Subtarget.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
@@ -21,9 +22,10 @@
 #include <iostream>
 using namespace llvm;
 
-SparcV8RegisterInfo::SparcV8RegisterInfo()
+SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
   : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
-                           V8::ADJCALLSTACKUP) {}
+                           V8::ADJCALLSTACKUP), Subtarget(st) {
+}
 
 void SparcV8RegisterInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
@@ -63,7 +65,8 @@
   else if (RC == V8::FPRegsRegisterClass)
     BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
   else if (RC == V8::DFPRegsRegisterClass)
-    BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg);
+    BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
+            1, DestReg).addReg(SrcReg);
   else
     assert (0 && "Can't copy this register");
 }
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.h b/lib/Target/SparcV8/SparcV8RegisterInfo.h
index 784a8e5..f739551 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.h
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.h
@@ -19,10 +19,13 @@
 
 namespace llvm {
 
+class SparcV8Subtarget;
 class Type;
 
 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
-  SparcV8RegisterInfo();
+  SparcV8Subtarget &Subtarget;
+  
+  SparcV8RegisterInfo(SparcV8Subtarget &st);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
diff --git a/lib/Target/SparcV8/SparcV8TargetMachine.cpp b/lib/Target/SparcV8/SparcV8TargetMachine.cpp
index 88f88f4..d868c10 100644
--- a/lib/Target/SparcV8/SparcV8TargetMachine.cpp
+++ b/lib/Target/SparcV8/SparcV8TargetMachine.cpp
@@ -35,7 +35,7 @@
                                            IntrinsicLowering *IL,
                                            const std::string &FS)
   : TargetMachine("SparcV8", IL, false, 4, 4),
-    Subtarget(M, FS),
+    Subtarget(M, FS), InstrInfo(Subtarget),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
 }