commit 69d555611aa1b7e45fc1b3719bfcb17a39dff9f3
author Evan Cheng <evan.cheng@apple.com> Wed May 23 07:22:05 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed May 23 07:22:05 2007 +0000
tree 2a199f74de228f160c9b97e35f951560f3a4cd23
parent d90733035d9ba66df97fc47d35f7eb3b2903f96c

Hooks for predication support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 186c3dd..ff717d9 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -298,11 +298,6 @@
   return NewMIs[0];
 }
 
-static bool isPredicated(MachineInstr *MI) {
-  MachineOperand *PMO = MI->findFirstPredOperand();
-  return PMO && PMO->getImmedValue() != ARMCC::AL;
-}
-
 // Branch analysis.
 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                                  MachineBasicBlock *&FBB,
@@ -436,23 +431,53 @@
   return false;
 }
 
+bool ARMInstrInfo::isPredicated(MachineInstr *MI) const {
+  MachineOperand *PMO = MI->findFirstPredOperand();
+  return PMO && PMO->getImmedValue() != ARMCC::AL;
+}
+
 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                      std::vector<MachineOperand> &Cond) const {
+                                      std::vector<MachineOperand> &Pred) const {
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
-    MI->addImmOperand(Cond[0].getImmedValue());
+    MI->addImmOperand(Pred[0].getImmedValue());
     return true;
   }
 
   MachineOperand *PMO = MI->findFirstPredOperand();
   if (PMO) {
-    PMO->setImm(Cond[0].getImmedValue());
+    PMO->setImm(Pred[0].getImmedValue());
     return true;
   }
   return false;
 }
 
+bool ARMInstrInfo::SubsumesPredicate(std::vector<MachineOperand> &Pred1,
+                                     std::vector<MachineOperand> &Pred2) const{
+  if (Pred1.size() > 1 || Pred2.size() > 1)
+    return false;
+
+  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
+  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
+  if (CC1 == CC2)
+    return true;
+
+  switch (CC1) {
+  default:
+    return false;
+  case ARMCC::AL:
+    return true;
+  case ARMCC::HS:
+    return CC2 == ARMCC::HI || CC2 == ARMCC::EQ;
+  case ARMCC::LS:
+    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
+  case ARMCC::GE:
+    return CC2 == ARMCC::GT || CC2 == ARMCC::EQ;
+  case ARMCC::LE:  return "le";
+    return CC2 == ARMCC::LT || CC2 == ARMCC::EQ;
+  }
+}
 
 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,

lib/Target/ARM/ARMInstrInfo.h

diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 84663e7..3f24c8b 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -104,8 +104,13 @@
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
 
   // Predication support.
+  virtual bool isPredicated(MachineInstr *MI) const;
+
   virtual bool PredicateInstruction(MachineInstr *MI,
-                                    std::vector<MachineOperand> &Cond) const;
+                                    std::vector<MachineOperand> &Pred) const;
+
+  virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
+                                 std::vector<MachineOperand> &Pred1) const;
 };
 
   // Utility routines