Fix newly-introduced 4.3 warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47375 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUFrameInfo.h b/lib/Target/CellSPU/SPUFrameInfo.h
index 91e4841..99136c2 100644
--- a/lib/Target/CellSPU/SPUFrameInfo.h
+++ b/lib/Target/CellSPU/SPUFrameInfo.h
@@ -34,7 +34,7 @@
getCalleeSaveSpillSlots(unsigned &NumEntries) const;
//! Stack slot size (16 bytes)
- static const int stackSlotSize() {
+ static int stackSlotSize() {
return 16;
}
//! Maximum frame offset representable by a signed 10-bit integer
@@ -42,19 +42,19 @@
This is the maximum frame offset that can be expressed as a 10-bit
integer, used in D-form addresses.
*/
- static const int maxFrameOffset() {
+ static int maxFrameOffset() {
return ((1 << 9) - 1) * stackSlotSize();
}
//! Minimum frame offset representable by a signed 10-bit integer
- static const int minFrameOffset() {
+ static int minFrameOffset() {
return -(1 << 9) * stackSlotSize();
}
//! Minimum frame size (enough to spill LR + SP)
- static const int minStackSize() {
+ static int minStackSize() {
return (2 * stackSlotSize());
}
//! Frame size required to spill all registers plus frame info
- static const int fullSpillSize() {
+ static int fullSpillSize() {
return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
}
//! Number of instructions required to overcome hint-for-branch latency
@@ -65,7 +65,7 @@
of instructions occurs between the HBR and the target. Currently, HBRs
take 6 cycles, ergo, the magic number 6.
*/
- static const int branchHintPenalty() {
+ static int branchHintPenalty() {
return 6;
}
};