Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24511 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index adb40af..eeda4f9 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -38,7 +38,13 @@
def f128 : ValueType<128, 10>; // 128-bit floating point value
def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
def isVoid : ValueType<0 , 12>; // Produces no value
-def Vector : ValueType<0 , 13>; // Abstract vector type
+def Vector : ValueType<0 , 13>; // Abstract vector value
+def v16i8 : ValueType<128, 14>; // 16 x i8 vector value
+def v8i16 : ValueType<128, 15>; // 8 x i16 vector value
+def v4i32 : ValueType<128, 16>; // 4 x i32 vector value
+def v2i64 : ValueType<128, 17>; // 2 x i64 vector value
+def v4f32 : ValueType<128, 18>; // 4 x f32 vector value
+def v2f64 : ValueType<128, 19>; // 2 x f64 vector value
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target