diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index cf26166..e21bf48 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1353,6 +1353,7 @@
         }
       }
 
+#if 0
       // If the LHS is '(and load, const)', the RHS is 0,
       // the test is for equality or unsigned, and all 1 bits of the const are
       // in the same partial word, see if we can shorten the load.
@@ -1401,7 +1402,8 @@
           }
         }
       }
-      
+#endif
+     
       // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
       if (N0.getOpcode() == ISD::ZERO_EXTEND) {
         unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();