Encode the register list operands for ARM mode LDM/STM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index f5d63a8..f1c54b9 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -197,6 +197,9 @@
unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
+ unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
+ const { return 0; }
+
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
/// machine operand requires relocation, record the relocation and return
/// zero.
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 141bc1a..91789da 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -937,17 +937,21 @@
string asm, string cstr, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
asm, cstr, pattern> {
+ bits<16> dsts;
let Inst{20} = 1; // L bit
let Inst{22} = 0; // S bit
let Inst{27-25} = 0b100;
+ let Inst{15-0} = dsts;
}
class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
asm, cstr, pattern> {
+ bits<16> srcs;
let Inst{20} = 0; // L bit
let Inst{22} = 0; // S bit
let Inst{27-25} = 0b100;
+ let Inst{15-0} = srcs;
}
// Unsigned multiply, multiply-accumulate instructions.
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 0a39000..4497a92 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -279,6 +279,7 @@
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
+ string EncoderMethod = "getRegisterListOpValue";
let PrintMethod = "printRegisterList";
}
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 8693ec3..b74fa73 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -98,6 +98,9 @@
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
+ unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
+
+
unsigned getNumFixupKinds() const {
assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
return 0;
@@ -285,6 +288,18 @@
return lsb | (msb << 5);
}
+unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
+ unsigned Op) const {
+ // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
+ // register in the list, set the corresponding bit.
+ unsigned Binary = 0;
+ for (unsigned i = Op; i < MI.getNumOperands(); ++i) {
+ unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
+ Binary |= 1 << regno;
+ }
+ return Binary;
+}
+
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {