Revert r121721, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 9434ecf..8066cb7 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -594,7 +594,7 @@
NegOk = true;
IsSoImm = true;
break;
- case ARM::t2ADR:
+ case ARM::t2LEApcrel:
Bits = 12;
NegOk = true;
break;
@@ -1555,7 +1555,7 @@
unsigned Bits = 0;
switch (Opcode) {
default: break;
- case ARM::t2ADR:
+ case ARM::t2LEApcrel:
if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
NewOpc = ARM::tLEApcrel;
Bits = 8;
@@ -1754,16 +1754,16 @@
if (!OptOk)
continue;
- // Now scan back again to find the tLEApcrel or t2ADR instruction
+ // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
// that gave us the initial base register definition.
for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
;
- // The instruction should be a tLEApcrel or t2ADR; we want
+ // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
// to delete it as well.
MachineInstr *LeaMI = PrevI;
if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
- LeaMI->getOpcode() != ARM::t2ADR) ||
+ LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
LeaMI->getOperand(0).getReg() != BaseReg)
OptOk = false;