commit 6c3b8ac6c9dfd7687a8097586925c09a84ab3d2e
author Evan Cheng <evan.cheng@apple.com> Mon Mar 08 23:28:08 2010 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Mar 08 23:28:08 2010 +0000
tree d5568a878947eb99d62f40df41d2506d0a912793
parent 57578766aa33d1a22cd124316df318db3e44f34a

Restrict machine cse to really trivial coalescing. Leave the heavy lifting to a real coalescer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98007 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineCSE.cpp

diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp
index b376e3d..ce8ebbc 100644
--- a/lib/CodeGen/MachineCSE.cpp
+++ b/lib/CodeGen/MachineCSE.cpp
@@ -91,7 +91,10 @@
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
     if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
         TargetRegisterInfo::isVirtualRegister(SrcReg) &&
+        MRI->getRegClass(SrcReg) == MRI->getRegClass(Reg) &&
         !SrcSubIdx && !DstSubIdx) {
+      DEBUG(dbgs() << "Coalescing: " << *DefMI);
+      DEBUG(dbgs() << "*** to: " << *MI);
       MO.setReg(SrcReg);
       DefMI->eraseFromParent();
       ++NumCoalesces;