commit 6c3daabc3ee51a8fcb804e0f110f01e59e0e6d61
author Kay Tiong Khoo <kkhoo@perfwizard.com> Tue Feb 12 00:19:12 2013 +0000
committer Kay Tiong Khoo <kkhoo@perfwizard.com> Tue Feb 12 00:19:12 2013 +0000
tree fcab8b8339070a35ecf1fc7d2418566b66876428
parent c951003faf4d475d221f5e839971673d2350b983

Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index b99a6eb..b00f7ea 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -119,6 +119,7 @@
 #define TWO_BYTE_EXTENSION_TABLES \
   EXTENSION_TABLE(00)             \
   EXTENSION_TABLE(01)             \
+  EXTENSION_TABLE(0d)             \
   EXTENSION_TABLE(18)             \
   EXTENSION_TABLE(71)             \
   EXTENSION_TABLE(72)             \