commit 6d5b7cc235e284130350045a320426afceb82874
author Jakob Stoklund Olesen <stoklund@2pi.dk> Tue Jan 03 22:34:35 2012 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Tue Jan 03 22:34:35 2012 +0000
tree 89735a749e2b2ad984d4762f6621eb5956a06ba7
parent 2d44e02533cdc2ae011121ef651dda93769ced2b

Revert r146997, "Heed spill slot alignment on ARM."

This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 13f1e66..dfd9c40 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -765,8 +765,7 @@
       break;
     case 16:
       if (ARM::QPRRegClass.hasSubClassEq(RC)) {
-        // Use aligned spills if the stack can be realigned.
-        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+        if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
           AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
                      .addFrameIndex(FI).addImm(16)
                      .addReg(SrcReg, getKillRegState(isKill))
@@ -915,7 +914,7 @@
     break;
   case 16:
     if (ARM::QPRRegClass.hasSubClassEq(RC)) {
-      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+      if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
         AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
                      .addFrameIndex(FI).addImm(16)
                      .addMemOperand(MMO));