Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 2537fc3..e2bbcfb 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3017,6 +3017,12 @@
(and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
Requires<[IsARM, HasV6]>;
+def : ARMV6Pat<(or (or (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
+ (and (shl GPR:$Rm, (i32 8)), 0xFF000000)),
+ (and (srl GPR:$Rm, (i32 8)), 0xFF)),
+ (and (shl GPR:$Rm, (i32 8)), 0xFF00)),
+ (REV16 GPR:$Rm)>;
+
def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "revsh", "\t$Rd, $Rm",
[(set GPR:$Rd,
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 53b9cec..cd077a8 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2593,6 +2593,12 @@
(or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
(and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
+def : T2Pat<(or (or (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
+ (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)),
+ (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
+ (and (shl rGPR:$Rm, (i32 8)), 0xFF00)),
+ (t2REV16 rGPR:$Rm)>;
+
def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
"revsh", ".w\t$Rd, $Rm",
[(set rGPR:$Rd,
diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll
index 5739086..c210a55 100644
--- a/test/CodeGen/ARM/rev.ll
+++ b/test/CodeGen/ARM/rev.ll
@@ -67,3 +67,20 @@
%or = or i32 %shr, %and
ret i32 %or
}
+
+; rdar://9609108
+define i32 @test6(i32 %x) nounwind readnone {
+entry:
+; CHECK: test6
+; CHECK: rev16 r0, r0
+ %and = shl i32 %x, 8
+ %shl = and i32 %and, 65280
+ %and2 = lshr i32 %x, 8
+ %shr11 = and i32 %and2, 255
+ %shr5 = and i32 %and2, 16711680
+ %shl9 = and i32 %and, -16777216
+ %or = or i32 %shr5, %shl9
+ %or6 = or i32 %or, %shr11
+ %or10 = or i32 %or6, %shl
+ ret i32 %or10
+}