Match tblgen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29895 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 22a99f2..2fb8a22 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -130,7 +130,8 @@
switch (ConstraintCode) {
default: return true;
case 'm': // memory
- AddToQueue(Op0, Op);
+ Op0 = Op;
+ AddToISelQueue(Op0);
break;
}
@@ -212,10 +213,12 @@
case AlphaISD::DivCall: {
SDOperand Chain = CurDAG->getEntryNode();
- SDOperand N0, N1, N2;
- AddToQueue(N0, Op.getOperand(0));
- AddToQueue(N1, Op.getOperand(1));
- AddToQueue(N2, Op.getOperand(2));
+ SDOperand N0 = Op.getOperand(0);
+ SDOperand N1 = Op.getOperand(1);
+ SDOperand N2 = Op.getOperand(2);
+ AddToISelQueue(N0);
+ AddToISelQueue(N1);
+ AddToISelQueue(N2);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
SDOperand(0,0));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
@@ -231,8 +234,8 @@
}
case ISD::READCYCLECOUNTER: {
- SDOperand Chain;
- AddToQueue(Chain, N->getOperand(0)); //Select chain
+ SDOperand Chain = N->getOperand(0);
+ AddToISelQueue(Chain); //Select chain
Result = SDOperand(CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
Chain), Op.ResNo);
return Result.Val;
@@ -300,9 +303,10 @@
case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
};
- SDOperand tmp1, tmp2;
- AddToQueue(tmp1, N->getOperand(0));
- AddToQueue(tmp2, N->getOperand(1));
+ SDOperand tmp1 = N->getOperand(0);
+ SDOperand tmp2 = N->getOperand(1);
+ AddToISelQueue(tmp1);
+ AddToISelQueue(tmp2);
SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
rev?tmp2:tmp1,
rev?tmp1:tmp2);
@@ -341,10 +345,13 @@
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N->getValueType(0) == MVT::f64;
- SDOperand LD, cond, TV, FV;
- AddToQueue(cond, N->getOperand(0));
- AddToQueue(TV, N->getOperand(1));
- AddToQueue(FV, N->getOperand(2));
+ SDOperand LD;
+ SDOperand cond = N->getOperand(0);
+ SDOperand TV = N->getOperand(1);
+ SDOperand FV = N->getOperand(2);
+ AddToISelQueue(cond);
+ AddToISelQueue(TV);
+ AddToISelQueue(FV);
if (AlphaLowering.hasITOF()) {
LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
@@ -385,10 +392,10 @@
mask = mask | dontcare;
if (get_zapImm(mask)) {
- SDOperand Src;
- AddToQueue(Src, N->getOperand(0).getOperand(0));
+ AddToISelQueue(N->getOperand(0).getOperand(0));
SDOperand Z =
- SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
+ SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
+ N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
getI64Imm(sval)), 0);
@@ -407,20 +414,19 @@
//TODO: add flag stuff to prevent nondeturministic breakage!
SDNode *N = Op.Val;
- SDOperand Chain;
+ SDOperand Chain = N->getOperand(0);
SDOperand Addr = N->getOperand(1);
SDOperand InFlag(0,0); // Null incoming flag value.
- AddToQueue(Chain, N->getOperand(0));
+ AddToISelQueue(Chain);
std::vector<SDOperand> CallOperands;
std::vector<MVT::ValueType> TypeOperands;
//grab the arguments
for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
- SDOperand Tmp;
TypeOperands.push_back(N->getOperand(i).getValueType());
- AddToQueue(Tmp, N->getOperand(i));
- CallOperands.push_back(Tmp);
+ AddToISelQueue(N->getOperand(i));
+ CallOperands.push_back(N->getOperand(i));
}
int count = N->getNumOperands() - 2;
@@ -464,7 +470,7 @@
Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
Addr.getOperand(0), Chain, InFlag), 0);
} else {
- AddToQueue(Addr, Addr);
+ AddToISelQueue(Addr);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index b82359d..f61c9e1 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -113,11 +113,13 @@
SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain, Tmp1, Tmp2;
- AddToQueue(Chain, N->getOperand(0));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Tmp1 = N->getOperand(0);
+ SDOperand Tmp2 = N->getOperand(1);
+ AddToISelQueue(Chain);
- AddToQueue(Tmp1, N->getOperand(0));
- AddToQueue(Tmp2, N->getOperand(1));
+ AddToISelQueue(Tmp1);
+ AddToISelQueue(Tmp2);
bool isFP=false;
@@ -308,12 +310,14 @@
default: break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
- SDOperand Chain;
+ SDOperand Chain = N->getOperand(0);
SDOperand InFlag; // Null incoming flag value.
- AddToQueue(Chain, N->getOperand(0));
- if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
- AddToQueue(InFlag, N->getOperand(2));
+ AddToISelQueue(Chain);
+ if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
+ InFlag = N->getOperand(2);
+ AddToISelQueue(InFlag);
+ }
unsigned CallOpcode;
SDOperand CallOperand;
@@ -334,8 +338,8 @@
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
- SDOperand FnDescriptor;
- AddToQueue(FnDescriptor, N->getOperand(1));
+ SDOperand FnDescriptor = N->getOperand(1);
+ AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
@@ -380,8 +384,8 @@
}
case IA64ISD::GETFD: {
- SDOperand Input;
- AddToQueue(Input, N->getOperand(0));
+ SDOperand Input = N->getOperand(0);
+ AddToISelQueue(Input);
Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
return Result.Val;
}
@@ -447,9 +451,10 @@
case ISD::LOAD:
case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
case ISD::ZEXTLOAD: {
- SDOperand Chain, Address;
- AddToQueue(Chain, N->getOperand(0));
- AddToQueue(Address, N->getOperand(1));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Address = N->getOperand(1);
+ AddToISelQueue(Chain);
+ AddToISelQueue(Address);
MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
@@ -487,9 +492,10 @@
case ISD::TRUNCSTORE:
case ISD::STORE: {
- SDOperand Address, Chain;
- AddToQueue(Address, N->getOperand(2));
- AddToQueue(Chain, N->getOperand(0));
+ SDOperand Address = N->getOperand(2);
+ SDOperand Chain = N->getOperand(0);
+ AddToISelQueue(Address);
+ AddToISelQueue(Chain);
unsigned Opc;
if (N->getOpcode() == ISD::STORE) {
@@ -501,8 +507,8 @@
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
- SDOperand Tmp;
- AddToQueue(Tmp, N->getOperand(1));
+ SDOperand Tmp = N->getOperand(1);
+ AddToISelQueue(Tmp);
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
Tmp), 0);
@@ -521,16 +527,18 @@
}
}
- SDOperand N1, N2;
- AddToQueue(N1, N->getOperand(1));
- AddToQueue(N2, N->getOperand(2));
+ SDOperand N1 = N->getOperand(1);
+ SDOperand N2 = N->getOperand(2);
+ AddToISelQueue(N1);
+ AddToISelQueue(N2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val;
}
case ISD::BRCOND: {
- SDOperand Chain, CC;
- AddToQueue(Chain, N->getOperand(0));
- AddToQueue(CC, N->getOperand(1));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand CC = N->getOperand(1);
+ AddToISelQueue(Chain);
+ AddToISelQueue(CC);
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
@@ -543,15 +551,15 @@
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
- SDOperand N0;
- AddToQueue(N0, N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0).Val;
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
- SDOperand N0;
- AddToQueue(N0, N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0).Val;
}
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index abb08dc..40f1005 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -124,7 +124,8 @@
break;
case 'o': // offsetable
if (!SelectAddrImm(Op, Op0, Op1)) {
- AddToQueue(Op0, Op); // r+0.
+ Op0 = Op;
+ AddToISelQueue(Op0); // r+0.
Op1 = getSmallIPtrImm(0);
}
break;
@@ -453,10 +454,10 @@
}
Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
- AddToQueue(Tmp1, Tmp3);
- AddToQueue(Tmp2, Op1);
+ AddToISelQueue(Tmp3);
+ AddToISelQueue(Op1);
SH &= 31;
- return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
+ return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp3, Op1,
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
}
}
@@ -692,7 +693,7 @@
SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
ISD::CondCode CC) {
// Always select the LHS.
- AddToQueue(LHS, LHS);
+ AddToISelQueue(LHS);
unsigned Opc;
if (LHS.getValueType() == MVT::i32) {
@@ -731,7 +732,7 @@
assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
Opc = PPC::FCMPUD;
}
- AddToQueue(RHS, RHS);
+ AddToISelQueue(RHS);
return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
}
@@ -804,8 +805,8 @@
// Check for those cases here.
// setcc op, 0
if (Imm == 0) {
- SDOperand Op;
- AddToQueue(Op, N->getOperand(0));
+ SDOperand Op = N->getOperand(0);
+ AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ:
@@ -831,8 +832,8 @@
}
}
} else if (Imm == ~0U) { // setcc op, -1
- SDOperand Op;
- AddToQueue(Op, N->getOperand(0));
+ SDOperand Op = N->getOperand(0);
+ AddToISelQueue(Op);
switch (CC) {
default: break;
case ISD::SETEQ:
@@ -928,8 +929,8 @@
}
case PPCISD::MFCR: {
- SDOperand InFlag;
- AddToQueue(InFlag, N->getOperand(1));
+ SDOperand InFlag = N->getOperand(1);
+ AddToISelQueue(InFlag);
// Use MFOCRF if supported.
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
@@ -946,8 +947,8 @@
// sra/addze rather than having to handle sdiv ourselves. oh well.
unsigned Imm;
if (isInt32Immediate(N->getOperand(1), Imm)) {
- SDOperand N0;
- AddToQueue(N0, N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ AddToISelQueue(N0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
@@ -978,14 +979,16 @@
SDOperand Val;
unsigned SH, MB, ME;
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
- AddToQueue(Val, N->getOperand(0).getOperand(0));
+ Val = N->getOperand(0).getOperand(0);
+ AddToISelQueue(Val);
} else if (Imm == 0) {
// AND X, 0 -> 0, not "rlwinm 32".
- AddToQueue(Result, N->getOperand(1));
+ AddToISelQueue(N->getOperand(1));
ReplaceUses(SDOperand(N, 0), N->getOperand(1));
return NULL;
} else {
- AddToQueue(Val, N->getOperand(0));
+ Val = N->getOperand(0);
+ AddToISelQueue(Val);
isRunOfOnes(Imm, MB, ME);
SH = 0;
}
@@ -1001,10 +1004,11 @@
unsigned MB, ME;
Imm = ~(Imm^Imm2);
if (isRunOfOnes(Imm, MB, ME)) {
- SDOperand Tmp1, Tmp2;
- AddToQueue(Tmp1, N->getOperand(0).getOperand(0));
- AddToQueue(Tmp2, N->getOperand(0).getOperand(1));
- return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
+ AddToISelQueue(N->getOperand(0).getOperand(0));
+ AddToISelQueue(N->getOperand(0).getOperand(1));
+ return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
+ N->getOperand(0).getOperand(0),
+ N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME));
}
}
@@ -1023,10 +1027,10 @@
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
- SDOperand Val;
- AddToQueue(Val, N->getOperand(0).getOperand(0));
+ AddToISelQueue(N->getOperand(0).getOperand(0));
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
- Val, getI32Imm(SH), getI32Imm(MB),
+ N->getOperand(0).getOperand(0),
+ getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME)).Val;
}
@@ -1037,10 +1041,10 @@
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
- SDOperand Val;
- AddToQueue(Val, N->getOperand(0).getOperand(0));
+ AddToISelQueue(N->getOperand(0).getOperand(0));
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
- Val, getI32Imm(SH), getI32Imm(MB),
+ N->getOperand(0).getOperand(0),
+ getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME)).Val;
}
@@ -1058,13 +1062,12 @@
N2C->getValue() == 1ULL && CC == ISD::SETNE &&
// FIXME: Implement this optzn for PPC64.
N->getValueType(0) == MVT::i32) {
- SDOperand LHS;
- AddToQueue(LHS, N->getOperand(0));
+ AddToISelQueue(N->getOperand(0));
SDNode *Tmp =
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
- LHS, getI32Imm(~0U));
+ N->getOperand(0), getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
- SDOperand(Tmp, 0), LHS,
+ SDOperand(Tmp, 0), N->getOperand(0),
SDOperand(Tmp, 1)).Val;
}
@@ -1084,26 +1087,26 @@
else
SelectCCOp = PPC::SELECT_CC_VRRC;
- SDOperand N2, N3;
- AddToQueue(N2, N->getOperand(2));
- AddToQueue(N3, N->getOperand(3));
+ AddToISelQueue(N->getOperand(2));
+ AddToISelQueue(N->getOperand(3));
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
- N2, N3, getI32Imm(BROpc)).Val;
+ N->getOperand(2), N->getOperand(3),
+ getI32Imm(BROpc)).Val;
}
case ISD::BR_CC: {
- SDOperand Chain;
- AddToQueue(Chain, N->getOperand(0));
+ AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
CondCode, getI32Imm(getBCCForSetCC(CC)),
- N->getOperand(4), Chain).Val;
+ N->getOperand(4), N->getOperand(0)).Val;
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
- SDOperand Chain, Target;
- AddToQueue(Chain, N->getOperand(0));
- AddToQueue(Target,N->getOperand(1));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Target = N->getOperand(1);
+ AddToISelQueue(Chain);
+ AddToISelQueue(Target);
unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
Chain), 0);
@@ -1130,15 +1133,18 @@
SmallVector<SDOperand, 8> Ops;
// Push varargs arguments, including optional flag.
for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- AddToQueue(Chain, N.getOperand(i));
+ Chain = N.getOperand(i);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
- AddToQueue(Chain, N.getOperand(0));
+ Chain = N.getOperand(0);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
if (hasFlag) {
- AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
+ Chain = N.getOperand(N.getNumOperands()-1);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
@@ -1170,13 +1176,16 @@
// Push varargs arguments, not including optional flag.
for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- AddToQueue(Chain, N.getOperand(i));
+ Chain = N.getOperand(i);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
- AddToQueue(Chain, N.getOperand(0));
+ Chain = N.getOperand(0);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
if (hasFlag) {
- AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
+ Chain = N.getOperand(N.getNumOperands()-1);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
return CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
@@ -1195,13 +1204,16 @@
// Push varargs arguments, not including optional flag.
for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- AddToQueue(Chain, N.getOperand(i));
+ Chain = N.getOperand(i);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
- AddToQueue(Chain, N.getOperand(0));
+ Chain = N.getOperand(0);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
if (hasFlag) {
- AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
+ Chain = N.getOperand(N.getNumOperands()-1);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
@@ -1221,13 +1233,16 @@
// Push varargs arguments, not including optional flag.
for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- AddToQueue(Chain, N.getOperand(i));
+ Chain = N.getOperand(i);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
- AddToQueue(Chain, N.getOperand(0));
+ Chain = N.getOperand(0);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
if (hasFlag) {
- AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
+ Chain = N.getOperand(N.getNumOperands()-1);
+ AddToISelQueue(Chain);
Ops.push_back(Chain);
}
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index fd22470..cb5ff8b 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -1076,9 +1076,10 @@
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
- SDOperand DivLHS, DivRHS;
- AddToQueue(DivLHS, N->getOperand(0));
- AddToQueue(DivRHS, N->getOperand(1));
+ SDOperand DivLHS = N->getOperand(0);
+ SDOperand DivRHS = N->getOperand(1);
+ AddToISelQueue(DivLHS);
+ AddToISelQueue(DivRHS);
// Set the Y register to the high-part.
SDOperand TopPart;
@@ -1099,9 +1100,10 @@
case ISD::MULHU:
case ISD::MULHS: {
// FIXME: Handle mul by immediate.
- SDOperand MulLHS, MulRHS;
- AddToQueue(MulLHS, N->getOperand(0));
- AddToQueue(MulRHS, N->getOperand(1));
+ SDOperand MulLHS = N->getOperand(0);
+ SDOperand MulRHS = N->getOperand(1);
+ AddToISelQueue(MulLHS);
+ AddToISelQueue(MulRHS);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);